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公开(公告)号：US6037623A
公开(公告)日：2000-03-14
申请号：US174869
申请日：1998-10-19
IPC分类号： H01L21/02 , H01L21/8244 , H01L27/11 , H01L29/00
CPC分类号： H01L28/20 , H01L27/11 , H01L27/1112 , Y10S257/903
摘要： A method for fabricating polycrystalline silicon resistor structures includes steps directed to the provision of a polycrystalline silicon structure having a decreased width. In one embodiment, sidewall spacers are used to narrow a region in which the polycrystalline silicon resistors are formed. In an alternative embodiment, polycrystalline silicon resistors are formed as sidewall structures in a resistor region. Use of either technique provides a reduced cross-section for the resistor structures, allowing shorter resistors to be used, or providing increased resistance for longer resistors.
摘要翻译： 一种用于制造多晶硅电阻器结构的方法包括提供具有减小的宽度的多晶硅结构的步骤。 在一个实施例中，使用侧壁间隔物来缩小其中形成多晶硅电阻器的区域。 在替代实施例中，多晶硅电阻器形成为电阻器区域中的侧壁结构。 使用这两种技术为电阻结构提供了一个减小的横截面，允许使用较短的电阻，或为较长的电阻提供增加的电阻。
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2.发明授权Contact structure for improving photoresist adhesion on a dielectric layer 失效用于改善介电层上的光致抗蚀剂粘附性的接触结构
公开(公告)号：US5877541A
公开(公告)日：1999-03-02
申请号：US905918
申请日：1997-08-04
IPC分类号： H01L23/532 , H01L23/58
CPC分类号： H01L23/5329 , H01L2924/0002 , Y10S257/90
摘要： A method is provided for improving the adhesion between a photoresist layer and a dielectric, and an integrated circuit formed according to the same. A conformal dielectric layer is formed over the integrated circuit. An interlevel dielectric layer is formed over the conformal dielectric layer. The interlevel dielectric layer is doped such that the doping concentration allows the layer to reflow while partially inhibiting the adhesion of the doped layer to photoresist at an upper surface of the doped layer. An undoped dielectric layer is formed over the doped dielectric layer. A photoresist layer is formed and patterned over the undoped dielectric layer which adheres to the undoped dielectric layer. The undoped dielectric, the interlevel dielectric and the conformal dielectric layers are etched to form an opening exposing a portion of an underlying conductive region.
摘要翻译： 提供了用于改善光致抗蚀剂层和电介质之间的粘合性的方法，以及根据该电路形成的集成电路。 在集成电路上形成保形介电层。 在保形电介质层上形成层间电介质层。 掺杂层间电介质层使得掺杂浓度允许层回流，同时部分地抑制掺杂层在掺杂层的上表面处的光致抗蚀剂的粘附。 在掺杂介电层上形成未掺杂的介电层。 在附着于未掺杂的介电层的未掺杂的电介质层上形成并图案化光致抗蚀剂层。 对未掺杂的电介质，层间电介质和共形绝缘层进行蚀刻以形成露出一部分下面的导电区域的开口。
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公开(公告)号：US5627104A
公开(公告)日：1997-05-06
申请号：US221071
申请日：1994-03-31
IPC分类号： H01L21/3105 , H01L21/768 , H01L21/44 , H01L21/48
CPC分类号： H01L21/31053 , H01L21/31051 , H01L21/76819
摘要： A method is provided for forming a substantially planarized surface of an integrated circuit, and an integrated circuit formed according to the same. A conductive area is formed over a portion of a dielectric region. A first spin-on-glass layer is formed over the conductive area and exposed dielectric region. A second spin-on-glass layer is formed over the first spin-on-glass layer; wherein the second spin-on-glass layer has a slower etch rate than the first spin-on-glass layer. A partial etchback of the first and second spin-on-glass layers is performed forming a substantially planar surface.
摘要翻译： 提供一种用于形成集成电路的基本上平坦化的表面的方法，以及根据该集成电路形成的集成电路。 在电介质区域的一部分上形成导电区域。 在导电区域和暴露的电介质区域上形成第一旋涂玻璃层。 在第一旋涂玻璃层上形成第二旋涂玻璃层; 其中所述第二旋涂玻璃层具有比所述第一旋涂玻璃层更慢的蚀刻速率。 执行第一和第二旋涂玻璃层的部分回蚀，形成基本平坦的表面。
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4.发明授权Method for fabricating a polycrystalline silicon resistive load element in an integrated circuit 失效在集成电路中制造多晶硅电阻性负载元件的方法
公开(公告)号：US5462894A
公开(公告)日：1995-10-31
申请号：US310925
申请日：1994-09-22
申请人： Charles R. Spinner , Fu-Tai Liou
发明人： Charles R. Spinner , Fu-Tai Liou
IPC分类号： H01L21/02 , H01L27/11 , H01L29/8605
CPC分类号： H01L28/20 , H01L27/1112 , Y10S148/136 , Y10S257/904
摘要： A method for forming integrated circuit structures includes the formation of high-value resistive elements and low resistance interconnect in a single polycrystalline layer. In one embodiment, interconnect regions of the polycrystalline silicon layer are masked, and resistive element regions are partially oxidized to reduce the thickness of the polycrystalline layer in such regions. Resistivity of the interconnect regions may then be reduced by implanting a high level of impurities in them, or by forming a refractory metal silicide layer over the interconnect regions. The oxide formed over the resistive elements during the oxidation thereof protects them from either of the following process steps, so that no masking is required. In an alternative embodiment, silicidation of the interconnect regions of the polycrystalline silicon layer may be performed without the prior local oxidations of the resistive element regions.
摘要翻译： 一种用于形成集成电路结构的方法包括在单个多晶层中形成高价值电阻元件和低电阻互连。 在一个实施例中，多晶硅层的互连区域被掩蔽，并且电阻元件区域被部分氧化以减小这些区域中的多晶层的厚度。 然后可以通过在其中注入高水平的杂质或通过在互连区域上形成难熔金属硅化物层来减小互连区域的电阻率。 在氧化过程中在电阻元件上形成的氧化物保护它们免于以下任一工艺步骤，从而不需要掩蔽。 在替代实施例中，多晶硅层的互连区域的硅化可以在电阻元件区域的先前局部氧化的情况下进行。
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5.发明授权Method for fabricating a polycrystalline silicon resistive load element in an integrated circuit 失效在集成电路中制造多晶硅电阻性负载元件的方法
公开(公告)号：US5268325A
公开(公告)日：1993-12-07
申请号：US741793
申请日：1991-08-06
IPC分类号： H01L21/02 , H01L21/768 , H01L23/532 , H01L27/11 , H01L21/70
CPC分类号： H01L28/20 , H01L21/76886 , H01L21/76889 , H01L23/53271 , H01L27/1112 , H01L2924/0002 , Y10S148/136
摘要： A method for forming integrated circuit structures includes the formation of high-value resistive elements and low resistance interconnect in a single polycrystalline layer. In one embodiment, interconnect regions of the polycrystalline silicon layer are masked, and resistive element regions are partially oxidized to reduce the thickness of the polycrystalline layer in such regions. Resistivity of the interconnect regions may then be reduced by implanting a high level of impurities in them, or by forming a refractory metal silicide layer over the interconnect regions. The oxide formed over the resistive elements during the oxidation thereof protects them from either of the following process steps, so that no masking is required. In an alternative embodiment, silicidation of the interconnect regions of the polycrystalline silicon layer may be performed without the prior local oxidations of the resistive element regions.
摘要翻译： 一种用于形成集成电路结构的方法包括在单个多晶层中形成高价值电阻元件和低电阻互连。 在一个实施例中，多晶硅层的互连区域被掩蔽，并且电阻元件区域被部分氧化以减小这些区域中的多晶层的厚度。 然后可以通过在其中注入高水平的杂质或通过在互连区域上形成难熔金属硅化物层来减小互连区域的电阻率。 在氧化过程中在电阻元件上形成的氧化物保护它们免于以下任一工艺步骤，从而不需要掩蔽。 在替代实施例中，多晶硅层的互连区域的硅化可以在电阻元件区域的先前局部氧化的情况下进行。
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公开(公告)号：US5825060A
公开(公告)日：1998-10-20
申请号：US869517
申请日：1992-04-16
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8244 , H01L27/11 , H01L27/108 , H01L29/76
CPC分类号： H01L28/20 , H01L27/11 , H01L27/1112
摘要： A resistor structure suitable for use in an SRAM cell is formed from polycrystalline silicon elements. These elements have a cross-section which is less than is normally available for polycrystalline silicon interconnect lines, allowing increased resistance values to be implemented using a lesser amount of surface area. In one embodiment of a resistor, sidewall spacers are formed in a cavity within an insulating layer, and polycrystalline silicon resistive elements are formed in the narrowed region within the cavity. In another embodiment, polycrystalline silicon resistors alongside vertical sidewalls of a cavity are formed using sidewall spacer technology. In either event, the cross-sectional area of the resistors is less than that normally available for a given processing technology, resulting in enhanced resistor values.
摘要翻译： 适用于SRAM单元的电阻结构由多晶硅元件形成。 这些元件具有小于通常可用于多晶硅互连线的横截面，允许使用较少量的表面积来实现增加的电阻值。 在电阻器的一个实施例中，侧壁间隔物形成在绝缘层内的空腔中，并且多晶硅电阻元件形成在空腔内的变窄区域中。 在另一个实施例中，使用侧壁间隔物技术形成沿着空腔的垂直侧壁的多晶硅电阻器。 在任一情况下，电阻器的横截面积小于通常用于给定处理技术的横截面积，导致增强的电阻值。
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公开(公告)号：US07534719B2
公开(公告)日：2009-05-19
申请号：US12082188
申请日：2008-04-09
IPC分类号： H01L21/4763
CPC分类号： H01L21/3212 , H01L21/7684
摘要： A protective barrier layer, formed of a material such as titanium or titanium nitride for which removal by chemical mechanical polishing (CMP) is primarily mechanical rather than primarily chemical, formed on a conformal tungsten layer. During subsequent CMP to pattern the tungsten layer, upper topological regions of the protective barrier layer (such as those overlying interlevel dielectric regions) are removed first, exposing the tungsten under those regions to removal, while protective barrier layer regions over lower topological regions (such as openings within the interlevel dielectric) remain to prevent chemical attack of underlying tungsten. CMP patterned tungsten is thus substantially planar with the interlevel dielectric without dishing, even in large area tungsten structures such as MOS capacitor structures.
摘要翻译： 由诸如钛或氮化钛的材料形成的保护性阻挡层，其通过化学机械抛光（CMP）的去除主要是机械的而不是主要是化学的，在保形钨层上形成。 在随后的CMP中对钨层进行图案化，首先去除保护性阻挡层（例如覆盖在层间介电区域上的那些层）的上部拓扑区域，将这些区域上的钨暴露出去除，同时保护性阻挡层区域在较低拓扑区域 作为层间电介质中的开口）保留以防止下层钨的化学侵蚀。 因此，即使在诸如MOS电容器结构的大面积钨结构中，CMP图案化钨也与层间电介质基本上是平面的。
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8.发明授权Barrier film deposition over metal for reduction in metal dishing after CMP 有权阻挡膜沉积在金属上以减少CMP后的金属凹陷公开(公告)号：US07372160B2
公开(公告)日：2008-05-13
申请号：US09871463
申请日：2001-05-31
IPC分类号： H01L23/52
CPC分类号： H01L21/3212 , H01L21/7684
摘要： A protective barrier layer, formed of a material such as titanium or titanium nitride for which removal by chemical mechanical polishing (CMP) is primarily mechanical rather than primarily chemical, formed on a conformal tungsten layer. During subsequent CMP to pattern the tungsten layer, upper topological regions of the protective barrier layer (such as those overlying interlevel dielectric regions) are removed first, exposing the tungsten under those regions to removal, while protective barrier layer regions over lower topological regions (such as openings within the interlevel dielectric) remain to prevent chemical attack of underlying tungsten. CMP patterned tungsten is thus substantially planar with the interlevel dielectric without dishing, even in large area tungsten structures such as MOS capacitor structures.
摘要翻译： 由诸如钛或氮化钛的材料形成的保护性阻挡层，其通过化学机械抛光（CMP）的去除主要是机械的而不是主要是化学的，在保形钨层上形成。 在随后的CMP中对钨层进行图案化，首先去除保护性阻挡层（例如覆盖在层间介电区域上的那些层）的上部拓扑区域，将这些区域上的钨暴露出去除，同时保护性阻挡层区域在较低拓扑区域 作为层间电介质中的开口）保留以防止下层钨的化学侵蚀。 因此，即使在诸如MOS电容器结构的大面积钨结构中，CMP图案化钨也与层间电介质基本上是平面的。
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公开(公告)号：US6010959A
公开(公告)日：2000-01-04
申请号：US152729
申请日：1998-09-14
IPC分类号： H01L23/532 , H01L29/34 , B44C1/22
CPC分类号： H01L23/5329 , H01L2924/0002 , Y10S257/90
摘要： A method is provided for improving the adhesion between a photoresist layer and a dielectric, and an integrated circuit formed according to the same. A conformal dielectric layer is formed over the integrated circuit. An interlevel dielectric layer is formed over the conformal dielectric layer. The interlevel dielectric layer is doped such that the doping concentration allows the layer to reflow while partially inhibiting the adhesion of the doped layer to photoresist at an upper surface of the doped layer. An undoped dielectric layer is formed over the doped dielectric layer. A photoresist layer is formed and patterned over the undoped dielectric layer which adheres to the undoped dielectric layer. The undoped dielectric, the interlevel dielectric and the conformal dielectric layers are etched to form an opening exposing a portion of an underlying conductive region.
摘要翻译： 提供了用于改善光致抗蚀剂层和电介质之间的粘合性的方法，以及根据该电路形成的集成电路。 在集成电路上形成保形介电层。 在保形电介质层上形成层间电介质层。 掺杂层间电介质层使得掺杂浓度允许层回流，同时部分地抑制掺杂层在掺杂层的上表面处的光致抗蚀剂的粘附。 在掺杂介电层上形成未掺杂的介电层。 在附着于未掺杂的介电层的未掺杂的电介质层上形成并图案化光致抗蚀剂层。 对未掺杂的电介质，层间电介质和共形绝缘层进行蚀刻以形成露出一部分下面的导电区域的开口。
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公开(公告)号：US5594269A
公开(公告)日：1997-01-14
申请号：US322387
申请日：1994-10-12
IPC分类号： H01L21/02 , H01L27/11 , H01L21/768 , H01L23/52
CPC分类号： H01L28/20 , H01L27/1112 , Y10S148/136 , Y10S257/904
摘要： An integrated circuit structure contains both highly resistive regions and highly conductive interconnect regions in a single layer of polycrystalline silicon. The resistive regions have a smaller cross section than the interconnect regions as a result of partial oxidation. Their thickness and width are reduced from that of the interconnect regions. The partial oxidation leaves an oxide region, derived from polycrystalline silicon, on both the top and sides of the resistive regions.
摘要翻译： 集成电路结构在单层多晶硅中包含高电阻区域和高导电互连区域。 由于部分氧化，电阻区域具有比互连区域更小的横截面。 它们的厚度和宽度比互连区域的厚度和宽度减小。 部分氧化在电阻区域的顶部和侧面留下来自多晶硅的氧化物区域。
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