公开(公告)号：US20070249121A1

公开(公告)日：2007-10-25

申请号：US11309206

申请日：2006-07-13

Applicant: Chien-Kang Kao ,  Chia-Ming Kuo ,  Chia-Lin Ku

Inventor： Chien-Kang Kao ,  Chia-Ming Kuo ,  Chia-Lin Ku

IPC: H01L21/336

CPC classification number: H01L21/28202 ,  B82Y10/00 ,  H01L29/40114 ,  H01L29/42332 ,  H01L29/518

Abstract: A method of fabricating a non-volatile memory is provided. The method includes providing a substrate. Next, a tunneling oxide layer is formed on the substrate and a surface nitridation process is performed to nitridize the upper surface of the tunneling oxide layer. A plurality of nanocrystals is formed on the nitridized surface of the tunneling oxide layer. Next, the surfaces of the nanocrystals are nitridized. An oxide layer and a conductive layer are formed in sequence over the tunneling oxide layer to cover the nanocrystals. Due to the formation of high-density nanocrystals as a charge storage medium, the properties of the memory are enhanced.

Abstract translation: 提供了一种制造非易失性存储器的方法。 该方法包括提供基板。 接下来，在基板上形成隧道氧化物层，进行表面氮化处理以使隧道氧化物层的上表面氮化。 在隧道氧化物层的氮化表面上形成多个纳米晶体。 接下来，将纳米晶体的表面氮化。 在隧道氧化物层上依次形成氧化物层和导电层以覆盖纳米晶体。 由于形成高密度纳米晶体作为电荷存储介质，因此存储器的性质得到提高。

公开(公告)号：US06171764B2

公开(公告)日：2001-01-09

申请号：US09138233

申请日：1998-08-22

Applicant: Chia-Lin Ku ,  Wen-Ping Yen

Inventor： Chia-Lin Ku ,  Wen-Ping Yen

IPC: G03C500

CPC classification number: H01L21/0276 ,  G03F7/091

Abstract: This invention provides methods for reducing the intensity of reflected rays encountered during the process of photolithography. By reducing the intensity of reflected ray, the pattern distortions associated with the interference from secondary rays can be minimized. In addition, this method for reducing the intensity of reflected ray can also eliminate the footing effect of other known methods in which the dielectric ARC layer is first deposited on the underlying layer, followed by the subsequent photolithography process of coating exposing, and developing.

Abstract translation: 本发明提供降低在光刻过程中遇到的反射光线的强度的方法。 通过降低反射光线的强度，可以将与来自二次射线的干涉相关联的图案畸变最小化。 另外，用于降低反射光线强度的方法也可以消除其中首先沉积介质ARC层的其它已知方法的基础效应，随后是随后的曝光和显影的光刻工艺。

公开(公告)号：US06764962B2

公开(公告)日：2004-07-20

申请号：US10162172

申请日：2002-06-05

Applicant: Yung-Hsien Wu ,  Chia-Lin Ku

Inventor： Yung-Hsien Wu ,  Chia-Lin Ku

IPC: H01L2131

CPC classification number: H01L21/02326 ,  H01L21/0214 ,  H01L21/02247 ,  H01L21/3144

Abstract: A method for forming oxynitride layer. The method includes (a) providing a substrate and removing the native oxide layer; (b) forming a nitride layer on the substrate; (c) oxidizing the nitride layer to form an oxynitride layer; and (d) subjecting the oxynitride layer to in-situ annealing. This method inhibits the penetration of boron into the substrate thereby improving the performance of semiconductor devices and production yield.

Abstract translation: 一种形成氮氧化物层的方法。 该方法包括（a）提供衬底并除去天然氧化物层; （b）在衬底上形成氮化物层; （c）氧化氮化物层以形成氧氮化物层; 和（d）使氮氧化物层进行原位退火。该方法抑制硼渗透到基板中，从而提高半导体器件的性能和生产率。

公开(公告)号：US06323137B1

公开(公告)日：2001-11-27

申请号：US09518233

申请日：2000-03-03

Applicant: Feng-Wei Ku ,  Chia-Lin Ku

Inventor： Feng-Wei Ku ,  Chia-Lin Ku

IPC: H01L2131

CPC classification number: C23C16/401 ,  H01L21/31604

Abstract: A method of forming an arsenic doped oxide layer in a process chamber is disclosed. The method comprises the steps of: setting the process chamber to a temperature of approximately 400-500° C. and a pressure of about 40-250 torr; flowing tetraethylorthosilicate (TEOS) into the process chamber; flowing triethylarsenate (TEAS or TEASAT) into the process chamber; and flowing ozone into the process chamber.

Abstract translation: 公开了一种在处理室中形成掺砷氧化物层的方法。 该方法包括以下步骤：将处理室设定为约400-500℃的温度和约40-250托的压力; 将原硅酸四乙酯（TEOS）流入工艺室; 将二乙基砷酸盐（TEAS或TEASAT）流入工艺室; 并将臭氧流入处理室。

公开(公告)号：US20050060108A1

公开(公告)日：2005-03-17

申请号：US10780729

申请日：2004-02-19

Applicant: Chia-Lin Ku

Inventor： Chia-Lin Ku

IPC: G01F15/06 ,  G01M3/28 ,  G06F19/00

CPC classification number: G01M3/2815 ,  G01F15/063

Abstract: The present invention is a field-measuring system and method supported by a PDA (Personal Digital Assistant) at the control processing field, comprising: a plurality of energy converters for sensing the processing variables at the control processing field and outputting the electric signals in response to the processing variables; a processing controller with a multi-port input interface for receiving the electric signals, processing the electric signals based on a single-chip microprocessor, and outputting the digital data corresponding to the processing variables; a personal digital assistant (PDA) for executing a driver to receive the digital data, and displaying the messages related to the processing variables; and a communication interface circuit for transmitting the data to a PDA. The combination of a PDA with a communication protocol technique facilitates the establishment of a real-time system for data retrieval and monitoring at a control processing field. In addition, the present invention improves the safety of the pipeline operation, and monitors the abnormalities of the pipelines around the clock by operating the pipe switch device at the field.

Abstract translation: 本发明是一种由控制处理领域的PDA（个人数字助理）支持的现场测量系统和方法，包括：多个能量转换器，用于感测控制处理场处的处理变量并输出响应的电信号 到处理变量; 处理控制器，具有用于接收电信号的多端口输入接口，基于单片微处理器处理电信号，并输出与处理变量对应的数字数据; 用于执行驱动程序以接收数字数据的个人数字助理（PDA），以及显示与处理变量相关的消息; 以及用于将数据发送到PDA的通信接口电路。 PDA与通信协议技术的组合有助于在控制处理领域建立用于数据检索和监视的实时系统。 此外，本发明提高了管道运行的安全性，并且通过在现场操作管道开关装置来监视全天候管道的异常。

公开(公告)号：US6156597A

公开(公告)日：2000-12-05

申请号：US94347

申请日：1998-06-09

Applicant: Wen-Ping Yen ,  Chia-Lin Ku ,  Chong-Che Lee

Inventor： Wen-Ping Yen ,  Chia-Lin Ku ,  Chong-Che Lee

IPC: H01L21/316 ,  H01L21/334 ,  H01L21/8242

CPC classification number: H01L29/66181 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/31612

Abstract: A method of fabricating a semiconductor device is provided including the steps of:(a) forming one or more protrusions on a semiconductor surface,(b) forming a first O.sub.x /TEOS film on top and side surfaces of the protrusions and surface area portions of the semiconductor surface separating the protrusions from each other, if any, and(c) forming a second O.sub.3 /TEOS film on, and covering, the first film.Illustratively, the protrusions have nitride regions at their peaks. The first film can be a low pressure (e.g., 30-70 torr) O.sub.3 /TEOS film or a plasma enhanced chemical vapor deposition (PECVD) O.sub.2 /TEOS film. The second film is a high pressure (e.g., 200-600 torr) O.sub.3 /TEOS film.The high pressure O.sub.3 /TEOS film avoids all of the disadvantages of the prior art. The low pressure O.sub.3 /TEOS film or PECVD O.sub.2 /TEOS film covers the nitride region of the protrusion so that the high pressure O.sub.3 /TEOS film will continuously cover the entire structure with a uniform thickness.

Abstract translation: 提供一种制造半导体器件的方法，包括以下步骤：（a）在半导体表面上形成一个或多个突起，（b）在凸起和表面区域的顶部和侧表面上形成第一Ox / TEOS膜 所述半导体表面将所述突起彼此分离（如果有的话），和（c）在所述第一膜上形成第二O 3 / TEOS膜并覆盖所述第一膜。 示例性地，突起在其峰处具有氮化物区域。 第一膜可以是低压（例如，30-70托）O 3 / TEOS膜或等离子体增强化学气相沉积（PECVD）O 2 / TEOS膜。 第二个膜是高压（例如，200-600托）O 3 / TEOS膜。 高压O3 / TEOS膜避免了现有技术的所有缺点。 低压O3 / TEOS膜或PECVD O2 / TEOS膜覆盖突起的氮化物区域，使得高压O 3 / TEOS膜将以均匀的厚度连续覆盖整个结构。

公开(公告)号：US5869406A

公开(公告)日：1999-02-09

申请号：US534901

申请日：1995-09-28

Applicant: Wen-Doe Su ,  Chia-Lin Ku

Inventor： Wen-Doe Su ,  Chia-Lin Ku

IPC: H01L21/316 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/31

CPC classification number: H01L27/1085 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76828 ,  Y10S438/909

Abstract: A method of fabricating an integrated circuit device with a substantially uniform inter-layer dielectric layer. The method includes steps of providing a partially completed semiconductor wafer (400) where the partially completed semiconductor device has a first polysilicon layer (401) thereon. The method includes depositing a dielectric layer (405) overlying the polysilicon layer and portions of the partially completed semiconductor device at a pressure of about 1 atmosphere. A step of forming a second polysilicon layer overlying portions of the dielectric layer is also included. The dielectric layer depositing step includes combining an organic silane and an ozone at a concentration of 200 g/m.sup.3 and less.

Abstract translation: 一种制造具有基本均匀的层间电介质层的集成电路器件的方法。 该方法包括提供部分完成的半导体晶片（400）的步骤，其中部分完成的半导体器件在其上具有第一多晶硅层（401）。 该方法包括在约1个大气压下沉积覆盖多晶硅层的电介质层（405）和部分完成的半导体器件的部分。 还包括形成覆盖介电层部分的第二多晶硅层的步骤。 电介质层沉积步骤包括以200g / m 3以下的浓度组合有机硅烷和臭氧。