公开(公告)号：US08815735B2

公开(公告)日：2014-08-26

申请号：US13463004

申请日：2012-05-03

Applicant: Yi Jung Chen ,  Kuo Hui Su ,  Chiang Hung Lin

Inventor： Yi Jung Chen ,  Kuo Hui Su ,  Chiang Hung Lin

IPC: H01L21/44

CPC classification number: H01L27/10855 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894

Abstract: A semiconductor device comprises a substrate, a dielectric layer, an undoped silicon layer, and a silicon material. The substrate comprises a doped region. The dielectric layer is formed on the substrate and comprises a contact hole, and the contact hole corresponds to the doped region. The undoped silicon layer is formed on the doped region. The silicon material fills the contact hole from the undoped silicon layer.

Abstract translation: 半导体器件包括衬底，电介质层，未掺杂的硅层和硅材料。 衬底包括掺杂区域。 电介质层形成在基片上并包括接触孔，接触孔对应于掺杂区域。 在掺杂区域上形成未掺杂的硅层。 硅材料从未掺杂的硅层填充接触孔。

公开(公告)号：US20130292799A1

公开(公告)日：2013-11-07

申请号：US13463004

申请日：2012-05-03

Applicant: Yi Jung CHEN ,  Kuo Hui Su ,  Chiang Hung Lin

Inventor： Yi Jung CHEN ,  Kuo Hui Su ,  Chiang Hung Lin

IPC: H01L29/00 ,  H01L21/20

CPC classification number: H01L27/10855 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894

Abstract: A semiconductor device comprises a substrate, a dielectric layer, an undoped silicon layer, and a silicon material. The substrate comprises a doped region. The dielectric layer is formed on the substrate and comprises a contact hole, and the contact hole corresponds to the doped region. The undoped silicon layer is formed on the doped region. The silicon material fills the contact hole from the undoped silicon layer.

Abstract translation: 半导体器件包括衬底，电介质层，未掺杂的硅层和硅材料。 衬底包括掺杂区域。 电介质层形成在基片上并包括接触孔，接触孔对应于掺杂区域。 在掺杂区域上形成未掺杂的硅层。 硅材料从未掺杂的硅层填充接触孔。

公开(公告)号：US07939421B2

公开(公告)日：2011-05-10

申请号：US12499622

申请日：2009-07-08

Applicant: Chiang Hung Lin

Inventor： Chiang Hung Lin

IPC: H01L21/76 ,  H01L21/44

CPC classification number: H01L21/76846 ,  H01L21/76856 ,  H01L21/76867

Abstract: A method for fabricating an integrated circuit structure includes the steps of forming a second dielectric layer on a substrate including a first conductive layer and a first dielectric layer, forming the second dielectric layer on the first conductive layer and the first dielectric layer, forming a hole exposing the first conductive layer in the second dielectric layer, forming a barrier layer inside the hole, and forming a second conductive layer on the barrier layer. In one embodiment of the present invention, the forming of the barrier layer comprises the steps of forming a metal layer in the hole, and performing a treating process in an atmosphere including a plasma formed from a gas including oxidant to form a metal oxide layer on the metal layer. In another embodiment of the present invention, the forming of the barrier layer comprises the steps of forming a metal nitride layer in the hole, and performing a treating process in an atmosphere including a plasma formed from a gas including oxidant to form a metal oxide layer on the metal and metal nitride layer.

Abstract translation: 一种用于制造集成电路结构的方法包括以下步骤：在包括第一导电层和第一介电层的基板上形成第二电介质层，在第一导电层和第一介电层上形成第二电介质层，形成孔 暴露第二介电层中的第一导电层，在孔内形成阻挡层，并在阻挡层上形成第二导电层。 在本发明的一个实施例中，阻挡层的形成包括以下步骤：在孔中形成金属层，并在包括由包含氧化剂的气体形成的等离子体的气氛中进行处理，以形成金属氧化物层 金属层。 在本发明的另一个实施例中，阻挡层的形成包括以下步骤：在孔中形成金属氮化物层，并在包括由包含氧化剂的气体形成的等离子体的气氛中进行处理，以形成金属氧化物层 在金属和金属氮化物层上。

公开(公告)号：US20140021535A1

公开(公告)日：2014-01-23

申请号：US13555640

申请日：2012-07-23

Applicant: Wen-Ping Liang ,  Chiang-Hung Lin ,  Kuo-Hui Su

Inventor： Wen-Ping Liang ,  Chiang-Hung Lin ,  Kuo-Hui Su

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66621 ,  H01L29/78

Abstract: A method for forming a semiconductor device with a vertical gate is disclosed, including providing a substrate, forming a recess in the substrate, forming a gate dielectric layer on a sidewall and a bottom of the recess, forming an adhesion layer in the recess and on the gate dielectric layer, wherein the adhesion layer is a metal silicide nitride layer, and forming a gate layer in the recess and on the adhesion layer.

Abstract translation: 公开了一种用于形成具有垂直栅极的半导体器件的方法，包括提供衬底，在衬底中形成凹槽，在凹槽的侧壁和底部上形成栅极电介质层，在凹部中形成粘附层， 所述栅介电层，其中所述粘附层是金属硅化物氮化物层，并且在所述凹部中和所述粘合层上形成栅极层。

公开(公告)号：US20130075812A1

公开(公告)日：2013-03-28

申请号：US13239389

申请日：2011-09-22

Applicant: Hsin-Jung Ho ,  Jeng-Ping Lin ,  Neng-Tai Shih ,  Chang-Rong Wu ,  Chiang-Hung Lin ,  Chih-Huang Wu

Inventor： Hsin-Jung Ho ,  Jeng-Ping Lin ,  Neng-Tai Shih ,  Chang-Rong Wu ,  Chiang-Hung Lin ,  Chih-Huang Wu

IPC: H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785

Abstract: A single-sided access device includes an active fin structure comprising a source contact area and a drain contact area separated from each other by an isolation region therebetween; a trench isolation structure disposed at one side of the active fin structure, wherein the trench isolation structure intersects with the isolation region between the source contact area and the drain contact area; a sidewall gate disposed under the isolation region and on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by the trench isolation structure and the sidewall gate, wherein the sidewall gate has multi-fingers that engage with the active fin structure; and a gate dielectric layer between the sidewall gate and the active fin structure.

Abstract translation: 单面存取装置包括活动鳍片结构，其包括源极接触区域和通过它们之间的隔离区域彼此分离的漏极接触区域; 沟槽隔离结构，设置在所述有源鳍结构的一侧，其中所述沟槽隔离结构与所述源极接触区域和所述漏极接触区域之间的隔离区域相交; 侧壁门，其设置在所述隔离区域下方并且在所述有源鳍结构的另一侧与所述沟槽隔离结构相对，使得所述有源鳍结构被所述沟槽隔离结构和所述侧壁栅极夹持，其中所述侧壁门具有多指 与活跃的鳍结构互动; 以及在侧壁浇口和活性鳍结构之间的栅介质层。

公开(公告)号：US08395209B1

公开(公告)日：2013-03-12

申请号：US13239389

申请日：2011-09-22

Applicant: Hsin-Jung Ho ,  Jeng-Ping Lin ,  Neng-Tai Shih ,  Chang-Rong Wu ,  Chiang-Hung Lin ,  Chih-Huang Wu

Inventor： Hsin-Jung Ho ,  Jeng-Ping Lin ,  Neng-Tai Shih ,  Chang-Rong Wu ,  Chiang-Hung Lin ,  Chih-Huang Wu

IPC: H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785

Abstract: A single-sided access device includes an active fin structure comprising a source contact area and a drain contact area separated from each other by an isolation region therebetween; a trench isolation structure disposed at one side of the active fin structure, wherein the trench isolation structure intersects with the isolation region between the source contact area and the drain contact area; a sidewall gate disposed under the isolation region and on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by the trench isolation structure and the sidewall gate, wherein the sidewall gate has multi-fingers that engage with the active fin structure; and a gate dielectric layer between the sidewall gate and the active fin structure.

Abstract translation: 单面存取装置包括活动鳍片结构，其包括源极接触区域和通过它们之间的隔离区域彼此分离的漏极接触区域; 沟槽隔离结构，设置在所述有源鳍结构的一侧，其中所述沟槽隔离结构与所述源极接触区域和所述漏极接触区域之间的隔离区域相交; 侧壁门，其设置在所述隔离区域下方并且在所述有源鳍结构的另一侧与所述沟槽隔离结构相对，使得所述有源鳍结构被所述沟槽隔离结构和所述侧壁栅极夹持，其中所述侧壁门具有多指 与活跃的鳍结构互动; 以及在侧壁浇口和活性鳍结构之间的栅介质层。

公开(公告)号：US20100279498A1

公开(公告)日：2010-11-04

申请号：US12815407

申请日：2010-06-15

Applicant: Yi-Jen Lo ,  Yu-Shan Chiu ,  Kuo-Hui Su ,  Chiang-Hung Lin

Inventor： Yi-Jen Lo ,  Yu-Shan Chiu ,  Kuo-Hui Su ,  Chiang-Hung Lin

IPC: H01L21/28

CPC classification number: H01L29/4983 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28105 ,  H01L21/28562 ,  H01L21/76852 ,  H01L23/53266 ,  H01L29/495 ,  H01L29/4966 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor structure is provided. The method includes providing a substrate; forming a dielectric layer on the substrate; forming a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and performing a selective atomic layer deposition (ALD) process to selectively deposit a conformal metal layer onto the top surface and sidewalls of the conductor pattern, but without depositing onto the main surface of the dielectric layer substantially.

Abstract translation: 提供一种形成半导体结构的方法。 该方法包括提供基板; 在基板上形成电介质层; 在所述电介质层的主表面上形成导体图案，所述导体图案具有顶表面和侧壁; 并且执行选择性原子层沉积（ALD）工艺以选择性地将共形金属层沉积到导体图案的顶表面和侧壁上，但是基本上不沉积到介电层的主表面上。

公开(公告)号：US20070125748A1

公开(公告)日：2007-06-07

申请号：US11295726

申请日：2005-12-07

Applicant: Yi-Jen Lo ,  Axel Buerke ,  Sven Schmidbauer ,  Chiang-Hung Lin

Inventor： Yi-Jen Lo ,  Axel Buerke ,  Sven Schmidbauer ,  Chiang-Hung Lin

IPC: G01L21/30 ,  C23F1/00 ,  H01L21/302 ,  B44C1/22

CPC classification number: H01L21/02186 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0234 ,  H01L21/2855 ,  H01L21/318 ,  H01L21/321 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76867

Abstract: A method for controlling a thickness of a first layer of an electrical contact of a semiconductor device, whereby the semiconductor device comprises a semiconductor layer, a first layer and a second layer, whereby at least a part of the semi-conductor layer is covered with the first layer, whereby at least a part of the first layer is covered with the second layer, whereby the second layer is exposed to a plasma gas, whereby an upper face of the first layer adjacent to the second layer is treated by the plasma gas and an interlayer is generated between the first and the second layer reducing the thickness of the first layer.

Abstract translation: 一种用于控制半导体器件的电接触的第一层的厚度的方法，由此所述半导体器件包括半导体层，第一层和第二层，由此半导体层的至少一部分被覆盖 第一层，其中第一层的至少一部分被第二层覆盖，由此第二层暴露于等离子体气体，由此与第二层相邻的第一层的上表面被等离子体气体 并且在第一和第二层之间产生中间层，从而减小第一层的厚度。

公开(公告)号：US06713745B2

公开(公告)日：2004-03-30

申请号：US10184123

申请日：2002-06-28

Applicant: Chiang Hung Lin

Inventor： Chiang Hung Lin

IPC: G01J132

CPC classification number: G01J1/44 ,  G01J1/32

Abstract: The present invention provides a display device with feedback brightness sensing, suitable for using in a PDA, that comprises a LCD panel at an outside of which is installed a first photo-sensor for sensing a light brightness variation of its environment. A corresponding sensing signal is delivered to a first converter to be converted to a first digital reference signal that is delivered to a microprocessor for determining a brightness increase or decrease of the display panel. Via a light-guiding element and a second photo-sensor installed within the display panel, the light brightness from the display panel is sensed and converted to a second digital reference signal that is compared with the first digital reference signal to determine whether the display brightness is at an optimal value. An automatic brightness adjustment of the display device is thereby achieved to reduce power consumption and protect the user's eyes.

Abstract translation: 本发明提供了一种具有反馈亮度感测的显示装置，其适用于在PDA中使用，其包括LCD面板，其外部安装有用于感测其环境的光亮度变化的第一光传感器。 将相应的感测信号传送到第一转换器以转换为第一数字参考信号，该第一数字参考信号被传送到微处理器以确定显示面板的亮度增加或减小。 通过安装在显示面板内的导光元件和第二光电传感器，来自显示面板的光亮度被感测并转换成与第一数字参考信号进行比较的第二数字参考信号，以确定显示亮度 处于最佳值。 由此实现显示装置的自动亮度调整，以降低功耗并保护用户的眼睛。

公开(公告)号：US06710318B2

公开(公告)日：2004-03-23

申请号：US10184122

申请日：2002-06-28

Applicant: Chiang Hung Lin

Inventor： Chiang Hung Lin

IPC: G01J132

CPC classification number: G01J1/32 ,  G01J1/44

Abstract: A brightness feedback display device includes a LCD panel, a plurality of first photo-sensors for sensing the environmental brightness variation of the display device itself. Corresponding sensing signals are delivered to first converters for being converted to first digital reference signals that are delivered to a microprocessor, thereby determining how much brightness of the display panel increases or decreases. Via a light-guiding element and a second photo-sensor installed within the display panel, the light brightness from the display panel is sensed and converted to a second digital reference signal that is compared with the first digital reference signals to determine whether the display brightness is at an optimal value.

Abstract translation: 亮度反馈显示装置包括LCD面板，用于感测显示装置本身的环境亮度变化的多个第一光传感器。 对应的感测信号被传送到第一转换器以被转换成被传送到微处理器的第一数字参考信号，由此确定显示面板的亮度有多少增加或减少。 通过安装在显示面板内的导光元件和第二光电传感器，来自显示面板的光亮度被感测并转换成与第一数字参考信号相比较的第二数字参考信号，以确定显示亮度 处于最佳值。