公开(公告)号：US20180053555A1

公开(公告)日：2018-02-22

申请号：US15786402

申请日：2017-10-17

申请人： Sau Ching Wong

发明人： Sau Ching Wong

IPC分类号： G11C16/12

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5644

摘要： Adaptive write operations for non-volatile memories select programming parameters according to monitored programming performance of individual memory cells. In one embodiment of the invention, programming voltage for a memory cell increases by an amount that depends on the time required to reach a predetermined voltage and then a jump in the programming voltage is added to the programming voltage required to reach the next predetermined voltage. The adaptive programming method is applied to the gate voltage of memory cells; alternatively, it can be applied to the drain voltage of memory cells along a common word line. A circuit combines the function of a program switch and drain voltage regulator, allowing independent control of drain voltage of selected memory cells for parallel and adaptive programming. Verify and adaptive read operations use variable word line voltages to provide optimal biasing of memory and reference cells during sensing.

公开(公告)号：US20180042697A1

公开(公告)日：2018-02-15

申请号：US15671784

申请日：2017-08-08

申请人： Julielynn Yee-Ching WONG

发明人： Julielynn Yee-Ching WONG ,  Anush Sushant AGARWAL ,  Gerald Joseph ENNETT ,  Sachin Hiral Paresh DOSHI

IPC分类号： A61C3/10 ,  A61C3/06 ,  A61C1/08 ,  A61C3/08

CPC分类号： A61C3/10 ,  A61C1/088 ,  A61C3/06 ,  A61C3/08

摘要： A multi-functional dental tool is provided which may be used for the dental filling of teeth after the removal of damage in the teeth. The dental tool comprises a forcep portion on one end and a burnisher tool on the other end. The burnisher tool portion comprises a flat burnisher and a ball burnisher, and a joint which connects the forcep portion and the burnisher tool portion. In an alternate embodiment, the dental tool comprises a penlight holder which can receive and secure a penlight, which provides illumination when performing the filling procedure, especially in situations in which an overhead light source is not readily available.

公开(公告)号：USD799702S1

公开(公告)日：2017-10-10

申请号：US29561452

申请日：2016-04-15

申请人： Julielynn Yee-Ching Wong ,  Jody Mou

设计人： Julielynn Yee-Ching Wong ,  Jody Mou

公开(公告)号：US09449682B2

公开(公告)日：2016-09-20

申请号：US14980631

申请日：2015-12-28

申请人： Sau Ching Wong

发明人： Sau Ching Wong

IPC分类号： G11C11/56 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5644

摘要： Adaptive write operations for non-volatile memories select programming parameters according to monitored programming performance of individual memory cells. In one embodiment of the invention, programming voltage for a memory cell increases by an amount that depends on the time required to reach a predetermined voltage and then a jump in the programming voltage is added to the programming voltage required to reach the next predetermined voltage. The adaptive programming method is applied to the gate voltage of memory cells; alternatively, it can be applied to the drain voltage of memory cells along a common word line. A circuit combines the function of a program switch and drain voltage regulator, allowing independent control of drain voltage of selected memory cells for parallel and adaptive programming. Verify and adaptive read operations use variable word line voltages to provide optimal biasing of memory and reference cells during sensing.

摘要翻译： 非易失性存储器的自适应写入操作根据各个存储单元的监视编程性能选择编程参数。 在本发明的一个实施例中，用于存储单元的编程电压增加取决于达到预定电压所需的时间的量，然后将编程电压中的跳变加到达到下一个预定电压所需的编程电压。 自适应编程方法适用于存储单元的栅极电压; 或者，其可以沿着公共字线施加到存储器单元的漏极电压。 电路结合了程序开关和漏极电压调节器的功能，允许独立控制所选存储单元的漏极电压用于并行和自适应编程。 验证和自适应读取操作使用可变字线电压，以在感测期间提供存储器和参考单元的最佳偏置。

公开(公告)号：US08527186B2

公开(公告)日：2013-09-03

申请号：US12877487

申请日：2010-09-08

申请人： Hoi Ching Wong ,  Madhusudhan Chellappa ,  Carlos Gamez

发明人： Hoi Ching Wong ,  Madhusudhan Chellappa ,  Carlos Gamez

IPC分类号： F02D41/14 ,  G06F19/00

CPC分类号： F02D41/0027 ,  F02D19/027 ,  F02D19/0647 ,  F02D19/0692 ,  F02D19/081 ,  F02D19/105 ,  F02D41/1402 ,  F02D41/1454 ,  F02D41/1458 ,  F02D2041/1432 ,  Y02T10/32 ,  Y02T10/36

摘要： A computer-implemented method is used to correct deviations between a predicted gas excess air ratio and a calculated excess air ratio in a dual fuel engine or other gas fueled compression ignition engine. The method includes determining gas excess air ratio for the engine based at least in part on at least one detected current operating parameter and calculating a predicted exhaust gas oxygen concentration engine based on the predicted gas excess air ratio. A time based filtered predicted exhaust gas oxygen concentration value may then be calculated and compared to a time-based filtered measured exhaust gas oxygen concentration value. The resultant oxygen concentration deviation value may be used to generate a corrected predicted gas excess air ratio.

摘要翻译： 使用计算机实现的方法来校正双燃料发动机或其它气体燃料压缩点火发动机中预测的气体过量空气比和计算的过量空气比之间的偏差。 该方法包括至少部分地基于至少一个检测到的当前操作参数来确定发动机的气体过量空气比，并且基于预测的气体过量空气比计算预测排气氧浓度发动机。 然后可以计算基于时间的过滤的预测废气氧浓度值，并将其与基于时间的过滤的测量废气氧浓度值进行比较。 所得到的氧浓度偏差值可用于产生经校正的预测气体过量空气比。

公开(公告)号：US07895129B2

公开(公告)日：2011-02-22

申请号：US10465352

申请日：2003-06-18

申请人： Brian A. Phillips ,  Chad M. Hurley ,  Greg Cervelli ,  Ki Ching Wong ,  Paul A. Martin ,  Steve Chen ,  Yu Pan

发明人： Brian A. Phillips ,  Chad M. Hurley ,  Greg Cervelli ,  Ki Ching Wong ,  Paul A. Martin ,  Steve Chen ,  Yu Pan

IPC分类号： G06Q99/00

CPC分类号： G06Q10/08 ,  G06Q10/083 ,  G06Q20/02 ,  G06Q20/12 ,  G06Q30/0619

摘要： An integrated shipping scheme enables seller users of a third-party payment service to facilitate shipping transactions in connection with payment transactions for items sold by the sellers. Shipping information is automatically gathered and/or entered by the seller via a computer interface hosted by the third-party payment service and sent “behind the scenes” to a selected shipping vendor. The shipping vendor processes the shipping information, and returns shipment data, including data to generate a shipping label. A web page containing the shipping label is then generated and served to a client operated by the seller and displayed on a browser screen, enabling the shipping label to be printed out by the seller. At the same time, electronic payment transfer operations are performed to effectively transfer payment from the seller directly to the shipping vendor via the third-party payment service in a manner that is transparent to both the seller and the shipping vendor.

摘要翻译： 集成运输计划使卖方的第三方支付服务的用户能够促进与卖方出售的物品的支付交易相关的运输交易。 运送信息由卖方通过由第三方支付服务托管的计算机界面自动收集和/或输入，并将其“幕后”发送给选定的运输供应商。 运输供应商处理运输信息，并返回装运数据，包括用于生成运输标签的数据。 然后，生成包含运送标签的网页并将其送达由卖方操作并由浏览器屏幕显示的客户端，从而使卖方能够打印出运输标签。 同时，执行电子支付转移操作，以便对卖方和运输供应商均透明的方式，通过第三方支付服务有效地将卖方的付款从卖方直接转发给运送供应商。

公开(公告)号：US07232729B1

公开(公告)日：2007-06-19

申请号：US10431321

申请日：2003-05-06

申请人： Nga-Ching Wong

发明人： Nga-Ching Wong

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L29/66825 ,  H01L29/7833

摘要： The present invention provides a method of fabricating a doped semiconductor region comprising selectively implanting a first impurity to form a shallow heavily doped region. The method further comprises selectively implanting the first impurity to also form a deep more heavily doped region, disposed laterally within the shallow heavily doped region and vertically within and below the shallow heavily doped region. In an optional feature of the present invention, the method further comprises selectively implanting a second impurity, wherein the doping profile of the deep more heavily doped region is graded.

摘要翻译： 本发明提供一种制造掺杂半导体区域的方法，包括选择性地注入第一杂质以形成浅重掺杂区域。 该方法还包括选择性地注入第一杂质以形成深度更重的掺杂区域，其横向设置在浅重掺杂区域内并且垂直地在浅重掺杂区域内和下方。 在本发明的可选特征中，该方法还包括选择性地注入第二杂质，其中深度更重掺杂区域的掺杂分布被分级。

公开(公告)号：US07151292B1

公开(公告)日：2006-12-19

申请号：US10342549

申请日：2003-01-15

申请人： Nga-Ching Wong

发明人： Nga-Ching Wong

IPC分类号： H01L29/76

CPC分类号： H01L29/7923 ,  G11C16/0475 ,  H01L29/66833

摘要： A charge trapping dielectric memory cell array comprises a plurality of parallel bit lines implanted within the lightly doped substrate. The parallel bit lines define a plurality of channel regions spaced there between and form a semiconductor junction there with. A plurality of parallel and spaced apart word lines are positioned above the surface of the substrate and separated from the substrate by a charge trapping dielectric. The plurality of parallel word lines are perpendicularly positioned with respect to the bit lines. Each channel region comprises a central counter doped channel region adjacent to a top surface of the substrate and vertically extending into the channel region to a depth less than the bit line depth and being spaced from each semiconductor junction by a pocket region.

摘要翻译： 电荷捕获介质存储单元阵列包括在轻掺杂衬底内注入的多个并行位线。 并行位线限定在其间隔开的多个沟道区，并在其间形成半导体结。 多个平行且间隔开的字线位于衬底的表面上方并且通过电荷俘获电介质与衬底分离。 多个平行字线相对于位线垂直定位。 每个沟道区域包括与衬底的顶表面相邻并且垂直延伸到沟道区的深度小于位线深度的深度的中心反相掺杂沟道区，并且通过一个凹穴区与每个半导体结隔开。

公开(公告)号：US07139192B1

公开(公告)日：2006-11-21

申请号：US10773659

申请日：2004-02-06

申请人： Sau Ching Wong

发明人： Sau Ching Wong

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3436 ,  G11C2211/5621 ,  G11C2211/5622

摘要： Write operations that simultaneously program multiple memory cells on the same word line in an MBPC or MLC non-volatile memory employ word line voltage variation, programming pulse width variation, and column line voltage variation to achieve uniform programming accuracy across a range of target threshold voltages. One type of write operation reaches target threshold voltages during respective time intervals and in each time interval uses programming parameters that optimize threshold voltage resolution for the target threshold voltage corresponding to that interval. During or at the end of write operations or the ends of each interval, remedial programming sequences can adjust the threshold voltages of memory cells that program slowly.

摘要翻译： 在MBPC或MLC非易失性存储器中同时编程同一字线上的多个存储器单元的写操作采用字线电压变化，编程脉宽变化和列线电压变化，以在目标阈值电压范围内实现均匀的编程精度 。 一种类型的写入操作在各个时间间隔期间达到目标阈值电压，并且在每个时间间隔中使用针对对应于该间隔的目标阈值电压优化阈值电压分辨率的编程参数。 在写入操作期间或结束时间间隔期间，补救编程序列可以调节缓慢编程的存储器单元的阈值电压。

公开(公告)号：US07099188B1

公开(公告)日：2006-08-29

申请号：US11151863

申请日：2005-06-13

申请人： Sau Ching Wong

发明人： Sau Ching Wong

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C7/06 ,  G11C5/14 ,  G11C7/00 ,  G11C7/02

CPC分类号： G11C11/5621 ,  G11C11/56 ,  G11C11/5642 ,  G11C2211/5634 ,  G11C2211/5645

摘要： Auto-tracking bit line reference schemes have common reference and normal word lines and generate a “½ cell current” reference by providing reference bit lines with pull-up devices having a different effective size from the pull-up devices for bit line or by programming reference cells to different levels. To provide a true “current mirror” connection of the pull-up devices of bit line and one or more reference bit lines, an additional bias bit line causes currents through the pull-up devices for the selected bit line and the reference bit lines to mirror current through the pull-up device for the bias bit line. Embodiments of the invention can be used with binary and multiple-bit-per cell memory and with a variety of sense amplifiers, memory array architectures, and memory cell structures.