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    Data access device for working with a computer of power off status
    2.
    发明授权
    Data access device for working with a computer of power off status 有权
    数据存取设备，用于处理断电状态的计算机

    公开(公告)号：US07509444B2

    公开(公告)日：2009-03-24

    申请号：US11225030

    申请日：2005-09-14

    Applicant: Chih-Yang Chiu ,  Ching-Chin Huang ,  Teng-Chieh Yang ,  Tsahn-Yih Chang ,  Yang-Chih Huang ,  Li-Hao Hsiao

    Inventor： Chih-Yang Chiu ,  Ching-Chin Huang ,  Teng-Chieh Yang ,  Tsahn-Yih Chang ,  Yang-Chih Huang ,  Li-Hao Hsiao

    IPC: G05B13/00

    CPC classification number: G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

    Abstract: This invention discloses a data access device for using in computer of power off status, which comprises a power multiplexer, a DC to DC converter, a serial bus signal to storage interface signal controller, a data storage interface signal multiplexer, and a controller. Therefore, if controller detects an external device wants to access data storage device of computer at power off, it will control power multiplexer to retrieve the standby power of the power device and process power transformation to provide a required power for driving the storage device, and by using serial bus signal to storage interface signal controller, external device can access the data from storage device at power off.

    Abstract translation: 本发明公开了一种在断电状态计算机中使用的数据存取装置，包括电源多路复用器，DC-DC转换器，串行总线信号到存储接口信号控制器，数据存储接口信号多路复用器和控制器。 因此，如果控制器检测到外部设备想要在断电时访问计算机的数据存储设备，则它将控制功率复用器以检索功率器件的待机功率并处理功率变换，以提供驱动存储设备所需的电源，以及 通过使用串行总线信号到存储接口信号控制器，外部设备可以在断电时从存储设备访问数据。

    Method and apparatus for selecting a nonblocked interrupt request
    5.
    发明授权
    Method and apparatus for selecting a nonblocked interrupt request 失效
    用于选择非阻塞中断请求的方法和装置

    公开(公告)号：US5905897A

    公开(公告)日：1999-05-18

    申请号：US822183

    申请日：1997-03-20

    Applicant: Hong-Chich Chou ,  Jerng-Cherng Fan ,  Won-Yih Lin ,  Ching-Chin Huang

    Inventor： Hong-Chich Chou ,  Jerng-Cherng Fan ,  Won-Yih Lin ,  Ching-Chin Huang

    IPC: G06F13/24 ,  G06F9/46

    CPC classification number: G06F13/24

    Abstract: An interrupt processing method and apparatus particularly well-suited for use in an interrupt controller of a multiprocessor system or device. Each of the interrupt requests has at least one destination processor associated therewith for servicing the interrupt request. An interrupt controller in accordance with the present invention applies latched interrupt requests to a priority compare tree which serves to prioritize received interrupt requests. A number of higher priority requests, including the highest priority request, are supplied to a destination selection circuit which includes an interrupt dispatcher which determines a processor to which the first priority interrupt request will be dispatched. Similar determinations are made for the remaining identified interrupt requests, but with the corresponding destination register contents masked to prevent processors already selected to receive a higher priority interrupt from being considered for a lower priority interrupt. The destination selection circuit attempts to determine a unique destination processor for each of the highest priority interrupt requests, such that these multiple interrupt requests can therefore be dispatched to different processors simultaneously. One or more of the interrupt requests may be "blocked" during a particular time period because all destination processors which could service the blocked requests are already processing other interrupts, performing higher priority tasks or are otherwise unavailable. These blocked interrupt requests are identified and the corresponding destination registers are masked such that the remaining non-blocked interrupt requests can be delivered to an available destination processor.

    Abstract translation: 一种特别适用于多处理器系统或设备的中断控制器的中断处理方法和装置。 每个中断请求具有与其相关联的至少一个目的处理器用于服务中断请求。 根据本发明的中断控制器将锁存的中断请求应用于优先级比较树，该优先级比较树用于优先接收中断请求。 包括最高优先级请求的多个较高优先级请求被提供给目的地选择电路，该目的地选择电路包括确定要发送第一优先中断请求的处理器的中断分派器。 对剩余的已识别中断请求进行了类似的确定，但是对应的目标寄存器内容被屏蔽，以防止已经选择接收到较高优先级中断的处理器被考虑用于较低优先级的中断。 目的地选择电路尝试为每个优先级最高的中断请求确定唯一的目的地处理器，使得这些多个中断请求可以同时被分派到不同的处理器。 一个或多个中断请求可能在特定时间段内被“阻塞”，这是因为可以为被阻塞的请求提供服务的所有目标处理器已经在处理其他中断，执行较高优先级的任务或者不可用。 这些被阻塞的中断请求被识别，并且相应的目的地寄存器被屏蔽，使得剩余的非阻塞中断请求可以被传送到可用的目的地处理器。

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