公开(公告)号：US20180152005A1

公开(公告)日：2018-05-31

申请号：US15696604

申请日：2017-09-06

Applicant: Oclaro Japan, Inc.

Inventor： Takeshi KITATANI ,  Koichiro ADACHI

IPC: H01S5/40 ,  H01S5/12 ,  H01S5/026

CPC classification number: H01S5/4087 ,  H01S5/02284 ,  H01S5/026 ,  H01S5/1231 ,  H01S5/22 ,  H01S5/2272 ,  H01S2304/00

Abstract: In the arrayed semiconductor optical device, a plurality of semiconductor optical devices including a first semiconductor optical device and a second semiconductor optical device are monolithically integrated on a semiconductor substrate, each of the semiconductor optical devices includes a first semiconductor layer having a multiple quantum well layer and a grating layer disposed on an upper side of the first semiconductor layer, a layer thickness of the first semiconductor layer of the first semiconductor optical device is thinner than a layer thickness of the first semiconductor layer of the second semiconductor optical device, and a height of the grating layer of the first semiconductor optical device is lower than a height of the grating layer of the second semiconductor optical device corresponding to difference in the layer thickness of the first semiconductor layer.

公开(公告)号：US20170331257A1

公开(公告)日：2017-11-16

申请号：US15594397

申请日：2017-05-12

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Christoph EICHLER ,  Andre SOMERS ,  Bernhard STOJETZ ,  Andreas LOEFFLER ,  Alfred LELL

IPC: H01S5/40 ,  H01S5/10 ,  H01L33/32 ,  H01L33/00 ,  H01S5/30 ,  H01L27/15

CPC classification number: H01S5/4087 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02617 ,  H01L27/153 ,  H01L33/0025 ,  H01L33/0075 ,  H01L33/0095 ,  H01L33/32 ,  H01L33/325 ,  H01S5/026 ,  H01S5/1053 ,  H01S5/1096 ,  H01S5/22 ,  H01S5/3013 ,  H01S5/32341 ,  H01S2304/00

Abstract: A light-emitting semiconductor chip (100) is provided, having a first semiconductor layer (1), which is at least part of an active layer provided for generating light and which has a lateral variation of a material composition along at least one direction of extent. Additionally provided is a method for producing a semiconductor chip (100).

公开(公告)号：US20170310076A1

公开(公告)日：2017-10-26

申请号：US15490528

申请日：2017-04-18

Applicant: The Board of Trustees of the University of Illinois

Inventor： Can Bayram ,  Richard Liu

IPC: H01S5/02 ,  H01S5/323 ,  H01L31/0304 ,  H01L29/20 ,  H01L33/32

CPC classification number: H01S5/0207 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/0254 ,  H01L21/02609 ,  H01L29/2003 ,  H01L31/03044 ,  H01L33/16 ,  H01L33/32 ,  H01S5/021 ,  H01S5/0218 ,  H01S5/3013 ,  H01S5/3031 ,  H01S5/32341 ,  H01S2301/173 ,  H01S2304/00 ,  H01S2304/04

Abstract: A device including a non-polarization material includes a number of layers. A first layer of silicon (100) defines a U-shaped groove having a bottom portion (100) and silicon sidewalls (111) at an angle to the bottom portion (100). A second layer of a patterned dielectric on top of the silicon (100) defines vertical sidewalls of the U-shaped groove. A third layer of a buffer covers the first layer and the second layer. A fourth layer of gallium nitride is deposited on the buffer within the U-shaped groove, the fourth layer including cubic gallium nitride (c-GaN) formed at merged growth fronts of hexagonal gallium nitride (h-GaN) that extend from the silicon sidewalls (111), wherein a deposition thickness (h) of the gallium nitride above the first layer of silicon (100) is such that the c-GaN completely covers the h-GaN between the vertical sidewalls.

公开(公告)号：US20170237230A1

公开(公告)日：2017-08-17

申请号：US15583176

申请日：2017-05-01

Applicant: Sharp Kabushiki Kaisha

Inventor： Yoshinobu KAWAGUCHI ,  Takeshi KAMIKAWA

IPC: H01S5/028 ,  H01S5/343 ,  H01S5/223

CPC classification number: H01S5/0287 ,  B82Y20/00 ,  H01L33/44 ,  H01S5/0021 ,  H01S5/028 ,  H01S5/0282 ,  H01S5/221 ,  H01S5/223 ,  H01S5/2231 ,  H01S5/34333 ,  H01S2304/00

Abstract: A nitride semiconductor light emitting device includes a first coat film of aluminum nitride or aluminum oxynitride formed at a light emitting portion and a second coat film of aluminum oxide formed on the first coat film. The thickness of the second coat film is at least 80 nm and at most 1000 nm. Here, the thickness of the first coat film is preferably at least 6 nm and at most 200 nm.

公开(公告)号：US09518337B2

公开(公告)日：2016-12-13

申请号：US14713894

申请日：2015-05-15

Applicant: MITSUBISHI CHEMICAL CORPORATION

Inventor： Yutaka Mikawa ,  Hideo Fujisawa ,  Kazunori Kamada ,  Hirobumi Nagaoka ,  Shinichiro Kawabata ,  Yuji Kagamitani

IPC: C01B21/06 ,  C30B29/40 ,  C30B7/10

CPC classification number: C30B29/406 ,  C01B21/0632 ,  C01P2004/50 ,  C01P2006/40 ,  C01P2006/90 ,  C30B7/105 ,  C30B29/403 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/02634 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/365 ,  H01L33/0075 ,  H01L33/025 ,  H01L33/32 ,  H01L33/325 ,  H01S5/3086 ,  H01S5/32341 ,  H01S2304/00 ,  Y02P20/544 ,  Y10T428/2982

Abstract: A high-quality nitride crystal can be produced efficiently by charging a nitride crystal starting material that contains tertiary particles having a maximum diameter of from 1 to 120 mm and formed through aggregation of secondary particles having a maximum diameter of from 100 to 1000 μm, in the starting material charging region of a reactor, followed by crystal growth in the presence of a solvent in a supercritical state and/or a subcritical state in the reactor, wherein the nitride crystal starting material is charged in the starting material charging region in a bulk density of from 0.7 to 4.5 g/cm3 for the intended crystal growth.

公开(公告)号：US20160036197A1

公开(公告)日：2016-02-04

申请号：US14881523

申请日：2015-10-13

Applicant: Sharp Kabushiki Kaisha

Inventor： Yoshinobu KAWAGUCHI ,  Takeshi Kamikawa

IPC: H01S5/00 ,  H01S5/343 ,  H01S5/223 ,  H01S5/028 ,  H01S5/22

CPC classification number: H01S5/0287 ,  B82Y20/00 ,  H01L33/44 ,  H01S5/0021 ,  H01S5/028 ,  H01S5/0282 ,  H01S5/221 ,  H01S5/223 ,  H01S5/2231 ,  H01S5/34333 ,  H01S2304/00

Abstract: A nitride semiconductor light emitting device includes a first coat film of aluminum nitride or aluminum oxynitride formed at a light emitting portion and a second coat film of aluminum oxide formed on the first coat film. The thickness of the second coat film is at least 80 nm and at most 1000 nm. Here, the thickness of the first coat film is preferably at least 6 nm and at most 200 nm.

Abstract translation: 氮化物半导体发光器件包括在第一涂膜上形成的在发光部分形成的氮化铝或氮氧化铝的第一涂膜和氧化铝的第二涂膜。 第二涂膜的厚度为80nm以上1000nm以下。 这里，第一涂膜的厚度优选为6nm以上200nm以下。

公开(公告)号：US09065239B2

公开(公告)日：2015-06-23

申请号：US13865143

申请日：2013-04-17

Applicant: Trilumina Corporation

Inventor： John R. Joseph ,  Kevin L. Lear

IPC: H01S5/024 ,  H01S5/042 ,  H01S5/022 ,  H01S5/183 ,  H01S5/42

CPC classification number: H01S5/02476 ,  H01S5/0224 ,  H01S5/02272 ,  H01S5/02469 ,  H01S5/0425 ,  H01S5/18313 ,  H01S5/18333 ,  H01S5/18391 ,  H01S5/423 ,  H01S2304/00

Abstract: A top emitting VCSEL array may be coupled to a separate heat spreading superstrate that may be positioned above the apertures of the array and that may be able to transmit the emitted beams through the heat spreading superstrate. The VCSEL devices in the array may be controlled by an electrical connection to a pattern of conductive elements positioned in close contact with, but electrically isolated from, the heat spreading superstrate. The conductive elements may electrically control one or more of the VCSEL devices to enable sectional control of the light output. The elements may also be arraigned in a ground-signal-ground or coplanar waveguide configuration to improve the frequency response of the array.

Abstract translation: 顶部发射VCSEL阵列可以耦合到可以位于阵列的孔的上方的单独的热扩散覆盖层，并且可以能够将发射的光束透射通过散热覆盖层。 阵列中的VCSEL器件可以通过电连接到与热扩散覆盖层紧密接触但与之隔离的导电元件的图案来控制。 导电元件可以电控制一个或多个VCSEL器件以实现光输出的分段控制。 这些元件也可以在接地信号 - 地面或共面波导配置中被提升，以改善阵列的频率响应。

公开(公告)号：US08962356B2

公开(公告)日：2015-02-24

申请号：US13796322

申请日：2013-03-12

Applicant: Canon Kabushiki Kaisha

Inventor： Katsuyuki Hoshino

IPC: H01L21/00 ,  H01L21/36 ,  H01S5/30 ,  H01S5/10 ,  G02B6/122 ,  B82Y20/00 ,  H01S5/183 ,  H01S5/343 ,  H01L21/02

CPC classification number: H01L21/36 ,  B82Y20/00 ,  G02B6/1225 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01S5/105 ,  H01S5/183 ,  H01S5/30 ,  H01S5/34333 ,  H01S2304/00

Abstract: Provided is a method of manufacturing a photonic crystal, including: a first step of forming, on a surface of a substrate, a protective mask for selective growth, the protective mask having an opening pattern opened therein; a second step of selectively growing a columnar semiconductor from an exposed portion of the surface of the substrate not having the mask formed thereon, laterally overgrowing the semiconductor layer on the mask, and embedding the mask; a third step of forming a photonic crystal in the semiconductor layer so that openings in the opening pattern and the one of pores and grooves which form the photonic crystal are at least partly overlapped each other when seen from a direction perpendicular to the surface of the substrate; a fourth step of removing at least part of the columnar semiconductor; and a fifth step of removing at least part of the mask.

Abstract translation: 提供一种制造光子晶体的方法，包括：第一步骤，在基板的表面上形成用于选择性生长的保护掩模，所述保护掩模具有在其中打开的开口图案; 从不具有形成在其上的掩模的衬底的表面的暴露部分选择性地生长柱状半导体的第二步骤，横向地使掩模上的半导体层过度成长并嵌入掩模; 在半导体层中形成光子晶体的第三步骤，使得当从垂直于衬底的表面的方向观察时，开口图案中的开口和形成光子晶体的孔和沟槽中的开口至少部分地彼此重叠 ; 去除所述柱状半导体的至少一部分的第四步骤; 以及除去所述面罩的至少一部分的第五步骤。

公开(公告)号：US20140116502A1

公开(公告)日：2014-05-01

申请号：US14125835

申请日：2012-06-13

Applicant: Seiji Samukawa

Inventor： Seiji Samukawa

IPC: H01L29/66 ,  H01L31/0352 ,  H01S5/343

CPC classification number: H01L29/66977 ,  B82Y10/00 ,  B82Y20/00 ,  B82Y40/00 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/32139 ,  H01L29/127 ,  H01L29/66 ,  H01L31/035218 ,  H01L31/076 ,  H01L31/078 ,  H01L51/0093 ,  H01S5/3412 ,  H01S5/343 ,  H01S2304/00 ,  Y02E10/548

Abstract: A quantum nanodot 3 is formed of a semiconductor and has an outer diameter in two-dimensional directions which is not more than twice a bore radius of an exciton in the semiconductor. A two-dimensional quantum nanodot array 1 has a structure that the quantum nanodots 3 are two-dimensionally and uniformly arranged with a spacing between the quantum nanodots 3 being 1 nm or more. The two-dimensional nanodot array 1 may include an intermediate layer 6 which is made of a semiconductor or an insulator and is filled between the quantum nanodot arrays 10. Since the quantum nanodots have high orientation and high density, a high quantum confinement effect is attained. Therefore, the quantum nanodot 3 made of Si produces direct transition type luminescence. It is possible to control an optical property and a transport property of the two-dimensional quantum nanodot array 10.

Abstract translation: 量子纳米点3由半导体形成，其二维方向的外径不超过半导体激子的孔半径的两倍。 二维量子纳米点阵列1具有量子纳米点3二维且均匀排列的结构，量子纳米点3之间的间隔为1nm以上。 二维纳米点阵列1可以包括由半导体或绝缘体制成并填充在量子纳米点阵列10之间的中间层6.由于量子纳米点具有高取向和高密度，因此获得高量子限制效应 。 因此，由Si制成的量子纳米点3产生直接转变型发光。 可以控制二维量子纳米点阵列10的光学特性和传输性质。

公开(公告)号：US20100260222A1

公开(公告)日：2010-10-14

申请号：US12662099

申请日：2010-03-31

Applicant: Naoki Jogan ,  Takahiro Arakida

Inventor： Naoki Jogan ,  Takahiro Arakida

IPC: H01L29/20 ,  H01L21/20 ,  H01S5/323

CPC classification number: H01L21/02546 ,  H01L21/02395 ,  H01L21/02579 ,  H01L21/0262 ,  H01S5/18311 ,  H01S5/18347 ,  H01S5/3054 ,  H01S5/32316 ,  H01S2304/00 ,  H01S2304/04

Abstract: A method of manufacturing a semiconductor layer with which inactivation of impurity is able to be inhibited by a simple method, a semiconductor layer in which inactivation of impurity is inhibited, a method of manufacturing a laser diode with which inactivation of impurity is able to be inhibited by a simple method, and a laser diode including a semiconductor layer in which inactivation of impurity is inhibited are provided. In the method of manufacturing a semiconductor layer, after a semiconductor layer is formed by epitaxial growth with the use of AsH3, supply of AsH3 is stopped without separately supplying new gas when process temperature is 500 deg C. or more.

Abstract translation: 通过简单的方法制造能够抑制杂质失活的半导体层的制造方法，抑制杂质失活的半导体层，能够抑制杂质失活的激光二极管的制造方法 通过简单的方法，提供了包含抑制杂质失活的半导体层的激光二极管。 在制造半导体层的方法中，在使用AsH3通过外延生长形成半导体层之后，当处理温度为500℃以上时，不间断地供给新气体而停止供给AsH3。