Abstract:
A transceiver having shared and discrete components forming a transmit path and a receive path configured to couple to a communication medium for establishing a multi-tone modulated communication channel thereon. The transceiver includes a line driver component on the transmit path. The line driver is configured to respond to a protocol determination and by configuring at least one of a transmit power level and a transmit bandwidth of the multi-tone modulated communication channel on the communication medium. The line driver includes a plurality of pre-amplifiers each exhibiting a combination of transmit power and bandwidth for amplification of a transmit signal modulated with a selected multi-tone modulation protocol. The line driver also includes a single output amplifier having an output coupled to the communication medium and an input switchably coupled to an output of a selected one of the plurality of pre-amplifiers in response to the protocol determination.
Abstract:
A line driver for coupling a data transceiver to a transmission line having a load impedance via a transformer with a turns ratio of 1:n includes an input port for receiving an input signal voltage from the data transceiver, an output port for supplying an output signal voltage to the transformer, and an amplifier circuit for amplifying the input signal voltage. The amplifier circuit includes a first output stage, a second output stage coupled to the output port, an output resistor coupled to the first output stage, a feedback path from the first output stage to an input of the amplifier circuit, and a line matching network coupled between the first output stage and the second output stage, for compensating variations in the load impedance, so that a synthesized output impedance of the line driver substantially matches an actual load impedance Z of the transmission line.
Abstract:
A read channel circuit of an optical disk reproducing apparatus is adapted to provide stability in servo control and reduce power consumption by revising the offset component of the circuit components after application of reference signals and then the offset component caused by pit depth resulting from signals read out in reproducing a data from an optical disk. The read channel circuit includes: a data converting section for amplifying signals input via different channels and converting them to digital data. A data reproducing section is provided for summing and waveform-equalizing the digital signals, detecting the phase difference between the waveform-equalized signals and reference sampling points, and generating a sampling clock frequency which is provided to the data converting section for compensating for the phase difference. A servo error signal detecting signal is provided for delaying the signals input from the data converting section by phases specified by the offset revision control signal and the pit depth revision control signal, summing the delayed signals into a plurality of signals, and generating the tracking error signals based on the comparison of phase differences between the summed signals.
Abstract:
A XDSL line card including an allocator for allocating power to the multi-tone modulated communications on each of the subscriber lines, and for selecting control parameters sufficient to effect communications on each of the subscriber lines at a power level proximate to an allocated power level therefore. The line card also includes configurable components coupled to one another to form a transmit path and a receive path to couple to the digital subscriber lines. The configurable components are responsive to the control parameters selected by the allocator to initialize multi-tone communications over each of the plurality of subscriber lines at a power level proximate the allocated power level.
Abstract:
An amplifier including complementary push and pull components, a bias component and a quiescent current balancer. The complementary push and pull components are serially coupled to one another between an electrical source and sink to generate an output signal at a common output terminal responsive to the input signal source. The bias component is coupled between the input signal source and the complementary push-pull components to bias the input signal to the push component and the input signal to the pull component by discrete amounts which reduce cross-over clipping exhibited in the output signal. The quiescent current balancer is coupled to the output terminal to balance quiescent currents in the push and the pull component at discrete levels which equilibrate amplification levels of the input signal generated by the push component and the pull component in the output signal at the output terminal.
Abstract:
A method and circuit control a quiescent current of an amplifier including a preamplifier, error amplifiers, and output devices driven by the error amplifiers, the error amplifiers having an input-referred offset voltage. The method includes (a) applying a calibration voltage to an input of the error amplifiers, (b) calibrating a quiescent current of the output devices by changing the calibration voltage so that the calibrated quiescent current has a predetermined current value, the calibration voltage corresponding to the calibrated quiescent current being set as a correction voltage, and (c) operating the amplifier with the correction voltage applied to the input of the error amplifiers. The circuit includes a correction voltage generator supplying a correction voltage to the error amplifier input, a quiescent current detector detecting the quiescent current, and a calibration circuit adjusting the correction voltage so that the quiescent current is calibrated to a predetermined current value.
Abstract:
A variable-gain amplifier circuit includes an input port, an output port, and first and second amplifiers coupled therebetween. The first amplifier includes a first amplifier path having a first amplification factor, effective when the input signal has a voltage level in a first range, and a second amplifier path having a second amplification factor greater than the first amplification factor, effective when the input signal has a voltage level in a second range including voltages of a first polarity greater than that in the first range. The second amplifier includes a third amplifier path having the first amplification factor, effective when the input signal has a voltage level in a third range, and a fourth amplifier path having the second amplification factor, effective when the input signal has a voltage level in a fourth range including voltages of a second polarity greater than that in the third range.
Abstract:
An apparatus and method for adaptively generating a tracking error signal according to a phase error generated due to a nonuniform depth of pits formed in an optical disk. The apparatus includes a first adder to output a first added signal (A+C) among optical detection signals A, B, C and D output by four elements for detecting light beams reflected from the optical disk, a second adder to output a second added signal (B+D) among the optical detection signals A, B, C and D, a multiplexer to receive the optical detection signals A, B, C and D, the first added signal (A+C), and the second added signal (B+D), and to select and output the signals (A+C) and (B+D), A and B, or C and D, a phase detector to determine a difference between the two signals output by the multiplexer, and output the difference as a tracking error signal and determine whether the tracking error signal is normal, and a selection controller to control selection of the multiplexer according to the result of the determination of the phase detector. Therefore, an optimal tracking error signal is obtained by selecting appropriate optical detection signals according to the phase error between the selected optical detection signals.
Abstract:
An error compensation circuit for compensating for a frequency error and a boost error of an IC chip having a filter and a boost circuit. The error compensation circuit includes a frequency compensation circuit, a boost compensation circuit, and a switch being switchable in response to a mode control signal. The frequency compensation circuit includes a first level detector to detect a level of a signal output from the filter; a first level comparator to compare an output level of the first level detector with a reference signal level; a first integrator to integrate an output of the first level comparator to generate a frequency error signal; and a first data converter and storage to convert the stored digital data into an analog frequency compensation signal in the normal signal processing mode, and provide the frequency compensation signal to the filter. The boost compensation circuit includes a second level detector to detect a level of a signal output from the boost circuit; a second level comparator to compare an output level of the second level detector with the reference signal level; a second integrator to integrate an output of the second level comparator to generate a boost error signal; and a second data converter and storage to convert the boost error signal into digital data, store the digital data, convert the stored digital data into an analog boost compensation signal in the normal signal processing mode, and provide the boost compensation signal to the boost circuit.
Abstract:
In a video processing system, a burst signal generating circuit receives a discontinuous burst signal and generates a continuous burst signal by using a phase locked loop. In the conventional video processing system, it is difficult to select a loop gain and loop bandwidth for generating a burst signal, since the performance characteristics of a phase locked loop are directly influenced by the presence of a sample and hold circuit in the phase locked loop. In order to solve this problem, in processing a digital video, a discontinuous burst signal is detected, and then during a burst signal, the phase locked loop operates by the discontinuous burst signal detected so that the continuous burst signal may be generated. When the burst signal is not present, the phase locked loop operates by a constant error value according to the continuous burst signal shifted 90 degrees in phase. Thereby, the continuous burst signal is generated.