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公开(公告)号：US08036293B1
公开(公告)日：2011-10-11
申请号：US12322002
申请日：2009-01-28
CPC分类号： H04B3/08 , H03G1/0088 , H04L25/0204 , H04L25/0264 , H04L25/03159 , H04L27/2601 , H04M11/062
摘要： A transceiver having shared and discrete components forming a transmit path and a receive path configured to couple to a communication medium for establishing a multi-tone modulated communication channel thereon. The transceiver includes a line driver component on the transmit path. The line driver is configured to respond to a protocol determination and by configuring at least one of a transmit power level and a transmit bandwidth of the multi-tone modulated communication channel on the communication medium. The line driver includes a plurality of pre-amplifiers each exhibiting a combination of transmit power and bandwidth for amplification of a transmit signal modulated with a selected multi-tone modulation protocol. The line driver also includes a single output amplifier having an output coupled to the communication medium and an input switchably coupled to an output of a selected one of the plurality of pre-amplifiers in response to the protocol determination.
摘要翻译： 具有形成发送路径的共享和离散组件的收发机和被配置为耦合到通信介质以在其上建立多音调调制通信信道的接收路径。 收发器包括发送路径上的线路驱动器组件。 线路驱动器被配置为响应协议确定并且通过在通信介质上配置多音调调制通信信道的发射功率电平和发射带宽中的至少一个来配置。 线路驱动器包括多个前置放大器，每个前置放大器各自表现出发射功率和带宽的组合，用于放大以所选择的多音调制协议调制的发射信号。 线路驱动器还包括具有耦合到通信介质的输出的单个输出放大器和响应于协议确定可切换地耦合到多个前置放大器中的所选择的一个的输出的输入。
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公开(公告)号：US08345859B2
公开(公告)日：2013-01-01
申请号：US12009196
申请日：2008-01-16
申请人： Sam Heidari , Sigurd Schelstraete , Aner Tennen , Elango Pakriswamy , Chun-Sup Kim , Luiz Felipe Fuks
发明人： Sam Heidari , Sigurd Schelstraete , Aner Tennen , Elango Pakriswamy , Chun-Sup Kim , Luiz Felipe Fuks
CPC分类号： H04M11/062
摘要： A XDSL line card including an allocator for allocating power to the multi-tone modulated communications on each of the subscriber lines, and for selecting control parameters sufficient to effect communications on each of the subscriber lines at a power level proximate to an allocated power level therefore. The line card also includes configurable components coupled to one another to form a transmit path and a receive path to couple to the digital subscriber lines. The configurable components are responsive to the control parameters selected by the allocator to initialize multi-tone communications over each of the plurality of subscriber lines at a power level proximate the allocated power level.
摘要翻译： 一种XDSL线路卡，包括用于为每个用户线路上的多音调调制通信分配功率的分配器，并且用于选择足以在接近分配的功率电平的功率电平上在每个用户线上进行通信的控制参数 。 线卡还包括彼此耦合的可配置组件以形成发送路径和接收到数字用户线路的接收路径。 可配置组件响应于由分配器选择的控制参数，以在接近分配的功率电平的功率电平上初始化多个用户线中的每一个上的多音通信。
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公开(公告)号：US20080170609A1
公开(公告)日：2008-07-17
申请号：US12009196
申请日：2008-01-16
申请人： Sam Heidari , Sigurd Schelstraete , Aner Tennen , Elango Pakriswamy , Chun-Sup Kim , Luiz Felipe Fuks
发明人： Sam Heidari , Sigurd Schelstraete , Aner Tennen , Elango Pakriswamy , Chun-Sup Kim , Luiz Felipe Fuks
IPC分类号： H04B1/38
CPC分类号： H04M11/062
摘要： A XDSL line card including an allocator for allocating power to the multi-tone modulated communications on each of the subscriber lines, and for selecting control parameters sufficient to effect communications on each of the subscriber lines at a power level proximate to an allocated power level therefore. The line card also includes configurable components coupled to one another to form a transmit path and a receive path to couple to the digital subscriber lines. The configurable components are responsive to the control parameters selected by the allocator to initialize multi-tone communications over each of the plurality of subscriber lines at a power level proximate the allocated power level.
摘要翻译： 一种XDSL线路卡，包括用于为每个用户线路上的多音调调制通信分配功率的分配器，并且用于选择足以在接近分配的功率电平的功率电平上在每个用户线上进行通信的控制参数 。 线卡还包括彼此耦合的可配置组件以形成发送路径和接收到数字用户线路的接收路径。 可配置组件响应于由分配器选择的控制参数，以在接近分配的功率电平的功率电平上初始化多个用户线中的每一个上的多音通信。
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公开(公告)号：US08947282B1
公开(公告)日：2015-02-03
申请号：US12931018
申请日：2011-01-20
IPC分类号： H03M1/78
摘要： A current controller includes impedance elements coupled to form at least one impedance ladder circuit which exhibits a fixed impedance at an input and current divider steps each differing in a current magnitude by a multiple of three with respect to the current magnitude in an adjacent less significant step. Single pole triple throw (SPTT) switchably couple an associated step in the impedance ladder circuit to one of three outputs. Three discrete current sources or sinks are each coupled to a corresponding one of the outputs of each of the SPTT switches. The digital driver is coupled to each control input of each SPTT switch to additively deliver selected ones of the stepped currents from each step of the impedance ladder circuit to a corresponding selected one of the current sources or sinks.
摘要翻译： 电流控制器包括被耦合以形成至少一个阻抗梯形电路的阻抗元件，该阻抗梯形电路在输入和电流分压器步骤中呈现固定阻抗，每个输入电流和电流分压器步骤在相邻的较不重要的步骤中相对于电流幅度在电流幅度上相差三倍 。 单极三掷（SPTT）可将阻抗梯形电路中的相关步骤切换到三个输出之一。 三个离散电流源或吸收器各自耦合到每个SPTT开关的相应输出之一。 数字驱动器耦合到每个SPTT开关的每个控制输入，以将来自阻抗梯形电路的每个步骤的选定的步进电流相加地递送到相应的所选电流源或汇。
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5.发明授权Method and circuit for enabling rapid flux reversal in the coil of a write head associated with a computer disk drive, or the like 失效用于实现与计算机磁盘驱动器相关联的写入头的线圈中的快速磁通反转的方法和电路等
公开(公告)号：US6166869A
公开(公告)日：2000-12-26
申请号：US928999
申请日：1997-09-12
CPC分类号： H03K17/04106 , G11B5/022 , H03K17/6872 , H03K2217/0045
摘要： An H-bridge for applying a current to a coil of a write head assembly for writing data to a magnetic media includes two pair of two switchable transistors. Each pair of transistors is connected between a supply voltage and a reference potential and is adapted to be connected to the coil between the transistors of each pair for turning the transistors turned on and off in a sequence to control the direction of current flow in the coil. The upper transistors of each pair serves a switching transistor, and the lower transistors provide a mirrored referenced current to the coil. A pair of capacitors are connected to a control element of a respective associated one of the lower transistors, and switching circuitry is connected to the capacitors to selectively connect each of the capacitors to inject current into the control element of the respective associated lower transistor when the respective associated lower transistor is turned on. Also disclosed is a technique for adjusting the amount of boost current injected into the lower transistors.
摘要翻译： 用于将电流施加到用于将数据写入磁介质的写头组件的线圈的H桥包括两对可切换晶体管。 每对晶体管连接在电源电压和参考电位之间，并且适于连接到每对晶体管之间的线圈，以顺序地导通和关断晶体管，以控制线圈中的电流方向 。 每对的上部晶体管用于开关晶体管，而下部晶体管提供了到线圈的镜像参考电流。 一对电容器连接到相应相关联的一个下部晶体管的控制元件，并且开关电路连接到电容器以选择性地连接每个电容器以将电流注入到相应的相关联的下部晶体管的控制元件中，当 相应的相关联的较低晶体管导通。 还公开了一种用于调节注入到下部晶体管的升压电流的量的技术。
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公开(公告)号：US06831799B2
公开(公告)日：2004-12-14
申请号：US09725356
申请日：2000-11-29
IPC分类号： G11B502
CPC分类号： H03F3/45089 , G11B5/012 , G11B5/02 , G11B5/09 , G11B2005/0016 , H03F2203/45318 , H03F2203/45394 , H03F2203/45544
摘要： A differential amplifier circuit for amplifying an input signal and for providing an output signal representative of the input signal includes first and second amplifier circuits, and first and second coupling circuits. The first and second amplifier circuits each include first and second transistors, a resistor, and a current generator. The first coupling circuit includes a transistor, a capacitor, and a current generator, and couples a first input signal node to the first transistor of the second amplifier circuit. The second coupling circuit includes a transistor, a capacitor, and a current generator, and couples a second input signal node to the first transistor of the first amplifier circuit.
摘要翻译： 用于放大输入信号并提供表示输入信号的输出信号的差分放大器电路包括第一和第二放大器电路以及第一和第二耦合电路。 第一和第二放大器电路各自包括第一和第二晶体管，电阻器和电流发生器。 第一耦合电路包括晶体管，电容器和电流发生器，并且将第一输入信号节点耦合到第二放大器电路的第一晶体管。 第二耦合电路包括晶体管，电容器和电流发生器，并且将第二输入信号节点耦合到第一放大器电路的第一晶体管。
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公开(公告)号：US06462600B2
公开(公告)日：2002-10-08
申请号：US09318320
申请日：1999-05-25
申请人： Elango Pakriswamy
发明人： Elango Pakriswamy
IPC分类号： H03L500
CPC分类号： H03F3/45556 , G11B5/012 , G11B20/10009 , G11B2005/0013 , G11B2005/0016 , G11B2005/0018 , H03F3/45089 , H03F2203/45418 , H03F2203/45424 , H03F2203/45594 , H03F2203/45702 , H03F2203/45722
摘要： A circuit includes a differential amplifier that generates a differential offset signal on its output terminals. The circuit also includes an offset compensator that has input terminals respectively coupled to the amplifier output terminals and a compensation terminal coupled to the differential amplifier. The compensator maintains the differential offset signal at a predetermined value, for example 0 V. When used in an integrated read-head preamplifier, such a circuit compensates for the nonzero head bias voltage, i.e., the preamplifier input offset voltage, without using a component that is external to the integrated preamplifier circuit.
摘要翻译： 电路包括在其输出端产生差分偏移信号的差分放大器。 电路还包括偏移补偿器，其具有分别耦合到放大器输出端子的输入端子和耦合到差分放大器的补偿端子。 补偿器将差分偏移信号保持在预定值，例如0V。当在集成读头前置放大器中使用时，这种电路补偿非零头偏置电压，即前置放大器输入偏移电压，而不使用组件 在集成前置放大器电路外部。
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公开(公告)号：US06259305B1
公开(公告)日：2001-07-10
申请号：US09258081
申请日：1999-02-25
申请人： Elango Pakriswamy
发明人： Elango Pakriswamy
IPC分类号： H03K1756
摘要： A circuit and method to drive an H-bridge circuit is disclosed. The H-bridge circuit uses NMOS transistors for both the upper and lower sets of transistors. An inductive head is coupled between the terminals of the transistors. When a logic signal is received, it is boosted with a circuit including a capacitor and is used to drive one of the upper transistors. The upper transistor selected to be driven is responsive to the logic signal. A corresponding lower transistor is also driven, forcing current through the inductive head in a first direction. When the logic signal is received that is the complement of the first logic signal, the other upper and lower transistors turn on, thereby driving current through the inductive head in the other direction. Since all of the transistors in the H-bridge circuit are NMOS transistors, boosted driving circuits are used to quickly change the direction of the flux through the inductive head.
摘要翻译： 公开了一种用于驱动H桥电路的电路和方法。 H桥电路使用NMOS晶体管用于上和下组晶体管。 感应头耦合在晶体管的端子之间。 当接收到逻辑信号时，用包括电容器的电路进行升压，并用于驱动上述晶体管之一。 被选择驱动的上部晶体管响应于逻辑信号。 还驱动相应的下部晶体管，迫使电流沿着第一方向通过感应头。 当接收到作为第一逻辑信号的补码的逻辑信号时，另一个上和下晶体管导通，从而在另一个方向上驱动电流通过感应头。 由于H桥电路中的所有晶体管都是NMOS晶体管，所以使用升压驱动电路来快速地改变通过感应头的磁通的方向。
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9.发明授权Method and circuit for enabling rapid flux reversal in the coil of a write head associated with a computer disk drive, or the like 失效用于实现与计算机磁盘驱动器相关联的写入头的线圈中的快速磁通反转的方法和电路等
公开(公告)号：US6052017A
公开(公告)日：2000-04-18
申请号：US928447
申请日：1997-09-12
CPC分类号： H03K17/04106 , G11B5/022 , H03K17/6872 , H03K2217/0045
摘要： A method and apparatus, for applying a current to a coil of a write head assembly of a disk drive, or the like, to cause the flux within the coil to rapidly reverse, has an H-bridge having two pair of two switchable transistors. Each pair of the transistors is connected between a supply voltage and a reference potential, and is adapted to be connected to the coil between the two transistors of each pair. The two transistors of the first pair may be connected to receive a control signal to turn on complementary transistors of the first and second pair of transistors to selectively control current flow in the coil in first or second directions. A reference current source supplies a reference current, and one of the transistors in each of the first and second pairs of transistors is connected when turned on to mirror the reference current to control the currents in the coil. First and second parallel transistors are connected in parallel respectively with the mirror transistors, the first and second parallel transistors being connected to be turned on respectively by the control signal and the inverted control signal concurrently with the respective mirror transistor. A pair of timing elements turn off respective ones of the parallel transistors after a predetermined time so that when the parallel transistors are turned on, the current in the coil overshoots a value established by the mirror transistors.
摘要翻译： 一种用于将电流施加到盘驱动器等的写入头组件的线圈上以使线圈内的磁通快速反转的方法和装置具有具有两对两个可切换晶体管的H桥。 每对晶体管连接在电源电压和参考电位之间，并且适于连接到每对两个晶体管之间的线圈。 第一对的两个晶体管可以被连接以接收控制信号以导通第一和第二对晶体管的互补晶体管，以选择性地控制在第一或第二方向上的线圈中的电流。 参考电流源提供参考电流，并且当导通时连接第一和第二对晶体管中的每个晶体管中的一个晶体管以反映参考电流以控制线圈中的电流。 第一和第二并联晶体管分别与镜晶体管并联连接，第一和第二并联晶体管分别通过控制信号和反相控制信号分别连接到相应的镜像晶体管。 一对定时元件在预定时间之后关闭并联晶体管的各个，使得当并联晶体管导通时，线圈中的电流超过由镜晶体管建立的值。
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公开(公告)号：US06512645B1
公开(公告)日：2003-01-28
申请号：US09393231
申请日：1999-09-09
申请人： Giuseppe Patti , Roberto Alini , Elango Pakriswamy
发明人： Giuseppe Patti , Roberto Alini , Elango Pakriswamy
IPC分类号： G11B509
摘要： A method and circuit are disclosed for controlling the write head of a magnetic disk storage device. The circuit includes a pull-up device coupled to a terminal of the write head, a current sink circuit which is coupled to the write head terminal and a bootstrap circuit coupled to the current sink circuit. When reversing the direction of current flow through the write head so that current is drawn from the write head from the write head terminal, the bootstrap circuit and the current sink circuit are activated. When the current in the write head nears and/or slightly surpasses the desired destination current level, the bootstrap circuit is deactivated and the pull-up device is thereafter immediately activated for a predetermined period of time.
摘要翻译： 公开了一种用于控制磁盘存储装置的写入头的方法和电路。 电路包括耦合到写头的端子的上拉装置，耦合到写入头端子的电流吸收电路和耦合到电流吸收电路的自举电路。 当逆向通过写入头的电流的方向使得电流从写入头从写入头抽出时，自举电路和电流吸收电路被激活。 当写头中的电流接近和/或稍微超过期望的目的地电流电平时，自举电路被去激活，然后上拉装置立即激活预定时间段。
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