公开(公告)号：US08274466B2

公开(公告)日：2012-09-25

申请号：US12397616

申请日：2009-03-04

Applicant: Thomas S. David ,  Douglas Piasecki

Inventor： Thomas S. David ,  Douglas Piasecki

IPC: G09G5/00 ,  G09G3/36

CPC classification number: G09G3/3611 ,  G06F3/0412 ,  G06F3/14 ,  G06F3/1423 ,  G09G3/3685 ,  G09G3/3696 ,  G09G2310/08 ,  G09G2330/02 ,  G09G2330/022

Abstract: An LCD controller includes at least one I/O pad for providing an LCD drive voltage in an LCD mode of operation. I/O pad logic drives the at least one I/O pad responsive to a provided bias voltage. Voltage selection logic selects a higher voltage between an LCD drive voltage and an externally provided system voltage as a first voltage. Bias voltage logic selects one of the system voltage or the first voltage as the bias voltage for the I/O pad logic. The system voltage is selected as the bias voltage for the I/O pad logic in a non-LCD mode of operation for the I/O pad and the first voltage is selected for the bias voltage for the I/O pad logic in the LCD mode of operation for the I/O pad.

Abstract translation: LCD控制器包括至少一个用于在LCD操作模式下提供LCD驱动电压的I / O焊盘。 I / O焊盘逻辑根据所提供的偏置电压驱动至少一个I / O焊盘。 电压选择逻辑选择LCD驱动电压和外部提供的系统电压之间的较高电压作为第一电压。 偏置电压逻辑选择系统电压或第一电压之一作为I / O焊盘逻辑的偏置电压。 在I / O焊盘的非LCD操作模式下，系统电压被选择为I / O焊盘逻辑的偏置电压，并且为LCD中的I / O焊盘逻辑的偏置电压选择第一个电压 I / O板的工作模式。

公开(公告)号：US07518325B2

公开(公告)日：2009-04-14

申请号：US11537420

申请日：2006-09-29

Applicant: Michael Keith Odland ,  Douglas Piasecki

Inventor： Michael Keith Odland ,  Douglas Piasecki

IPC: H02P1/00

CPC classification number: H02P3/08 ,  H02H3/006 ,  H02H7/0851

Abstract: A system and method for an anti-pinch powered window system includes a window and a mechanical drive mechanism for raising and lowering the window. An electric motor drives the mechanical drive mechanism responsive to a command. A microcontroller unit generates the command responsive to a measured load current of the electric motor. A command to change direction of the window is generated responsive to a determination that the measured load current has exceeded a variable threshold level indicating that the window has stopped due to an obstruction. The variable threshold level is determined by the load current data stored within a memory.

Abstract translation: 一种用于防夹闭动力窗系统的系统和方法，包括窗和用于升高和降低窗的机械驱动机构。 电动机响应于命令驱动机械驱动机构。 微控制器单元响应于电动机的测量负载电流产生该命令。 响应于测量的负载电流已经超过指示窗口由于阻塞停止的可变阈值电平的确定而产生改变窗口方向的命令。 可变阈值电平由存储在存储器内的负载电流数据确定。

公开(公告)号：US07504902B2

公开(公告)日：2009-03-17

申请号：US11618581

申请日：2006-12-29

Applicant: Douglas Piasecki ,  Douglas Holberg

Inventor： Douglas Piasecki ,  Douglas Holberg

IPC: H03L1/04 ,  G06F1/00

CPC classification number: H03K3/0231 ,  H03K3/356113 ,  H03K5/2481

Abstract: The integrated system on a chip with LINBUS network communication capabilities includes processing circuitry for performing predefined digital processing functionalities on the chip. A free running clock circuit generates a temperature compensated clock that does not require a synch signal from external to the chip. A LINBUS network communications interface digitally communicates with off-chip LINBUS devices. Communication between said on-chip LINBUS communications interface and the off-chip LINBUS devices is affected without clock recovery. The LINBUS network communication interface has a time base derived from the temperature compensated clock which is independent of any timing information in the input data received during a receive operation. The temperature compensated clock further provides an on-chip time reference for both the processing circuitry and the LINBUS network communications interface.

Abstract translation: 具有LINBUS网络通信能力的芯片上的集成系统包括用于在芯片上执行预定义的数字处理功能的处理电路。 自由运行的时钟电路产生温度补偿时钟，不需要来自芯片外部的同步信号。 LINBUS网络通信接口与片外LINBUS设备进行数字通信。 所述片上LINBUS通信接口和片外LINBUS器件之间的通信不受时钟恢复的影响。 LINBUS网络通信接口具有从温度补偿时钟导出的时基，其独立于在接收操作期间接收的输入数据中的任何定时信息。 温度补偿时钟还为处理电路和LINBUS网络通信接口提供片上时间参考。

公开(公告)号：US20070216548A1

公开(公告)日：2007-09-20

申请号：US11694624

申请日：2007-03-30

Applicant: DONALD ALFANO ,  DANNY ALLRED ,  DOUGLAS PIASECKI ,  KENNETH FERNALD ,  KA LEUNG ,  BRIAN CALOWAY ,  ALVIN STORVIK ,  PAUL HIGHLEY ,  DOUGLAS HOLBERG

Inventor： DONALD ALFANO ,  DANNY ALLRED ,  DOUGLAS PIASECKI ,  KENNETH FERNALD ,  KA LEUNG ,  BRIAN CALOWAY ,  ALVIN STORVIK ,  PAUL HIGHLEY ,  DOUGLAS HOLBERG

IPC: H03M7/00

CPC classification number: G06F13/385 ,  G06F1/08 ,  G06F15/7814 ,  H03M1/122 ,  H03M1/183 ,  H03M1/462 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: An integrated circuit package includes a processing core and an internal oscillator. The processing core operates on a set of instructions to carry out predefined processes. The internal oscillator provides a system clock for the integrated circuit package. The internal oscillator has associated therewith an internal control register for controlling the operation of the internal oscillator responsive to control bits of the internal oscillator controlled by the processing core.

Abstract translation: 集成电路封装包括处理核心和内部振荡器。 处理核心通过一组指令来执行预定义的过程。 内部振荡器为集成电路封装提供系统时钟。 内部振荡器具有与其相关联的内部控制寄存器，用于响应于由处理核心控制的内部振荡器的控制位来控制内部振荡器的操作。

公开(公告)号：US06950047B1

公开(公告)日：2005-09-27

申请号：US10816436

申请日：2004-03-31

Applicant: Douglas Piasecki ,  James Dub Austin ,  Douglas Holberg ,  Kenneth Fernald

Inventor： Douglas Piasecki ,  James Dub Austin ,  Douglas Holberg ,  Kenneth Fernald

IPC: H03M1/00 ,  H03M1/20 ,  H03M1/68 ,  H03M1/74

CPC classification number: H03M1/68 ,  H03M1/742

Abstract: Method and apparatus for combining outputs of multiple DACs for increased bit resolution. A method for providing an increased bit resolution to a data converter operable to convert digital information to analog values. A first current Digital-to-Analog (IDAC) converter is controlled to provide current to a first output node, the first IDAC having a first current step size associated with the Least Significant Bit (LSB) thereof. A second IDAC is controlled to provide current to the first output node, the second IDAC having a second current step size associated with the LSB thereof that is smaller than the first current step size. The combination of the first and second IDACs increases the bit resolution of the first IDAC when driving the first output node with the second IDAC.

Abstract translation: 用于组合多个DAC的输出以提高比特分辨率的方法和装置。 一种用于向可操作以将数字信息转换为模拟值的数据转换器提供增加的位分辨率的方法。 控制第一当前数模（IAC）转换器以向第一输出节点提供电流，第一IDAC具有与其最低有效位（LSB）相关联的第一当前步长。 控制第二IDAC以向第一输出节点提供电流，第二IDAC具有与其LSB的相关联的小于第一当前步长的第二当前步长。 当用第二IDAC驱动第一输出节点时，第一和第二IDAC的组合增加了第一IDAC的位分辨率。

公开(公告)号：US06922164B1

公开(公告)日：2005-07-26

申请号：US10815416

申请日：2004-03-31

Applicant: Douglas Piasecki ,  Douglas Holberg ,  Ka Y. Leung ,  Donald E. Alfano

Inventor： Douglas Piasecki ,  Douglas Holberg ,  Ka Y. Leung ,  Donald E. Alfano

IPC: H03M1/34 ,  H03M1/46

CPC classification number: H03M1/462

Abstract: SAR analog-to-digital converter with abort function. A method for increasing the throughput of a data converter decision is disclosed. First, a data conversion operation is initiated to convert analog signals on an analog input on a data converter to digital data by sampling the analog signals on the analog signal input and then converting the sampled analog signals to digital data with a predetermined data conversion algorithm in a data conversion operation. The digital output of the data converter is compared to a threshold voltage value. When the output of the data converter is determined by the step of comparing to meet a predetermined relationship relative to the threshold voltage, the data conversion operation is terminated prior to the complete execution of the data conversion operation on the sampled analog signals.

Abstract translation: 具有中止功能的SAR模数转换器。 公开了一种用于增加数据转换器决定的吞吐量的方法。 首先，通过对模拟信号输入上的模拟信号进行采样，然后利用预定的数据转换算法将采样的模拟信号转换成数字数据，开始数据转换操作以将数据转换器上的模拟输入上的模拟信号转换成数字数据 数据转换操作。 将数据转换器的数字输出与阈值电压值进行比较。 当通过比较步骤确定数据转换器的输出以达到相对于阈值电压的预定关系时，在对采样的模拟信号完成数据转换操作之后终止数据转换操作。

公开(公告)号：US20100328286A1

公开(公告)日：2010-12-30

申请号：US12495600

申请日：2009-06-30

Applicant: DOUGLAS PIASECKI ,  THOMAS S. DAVID ,  TIMOTHY THOMAS RUEGER ,  STEFAN MASTOVICH ,  JIA-HAU LIU

Inventor： DOUGLAS PIASECKI ,  THOMAS S. DAVID ,  TIMOTHY THOMAS RUEGER ,  STEFAN MASTOVICH ,  JIA-HAU LIU

IPC: G09G5/00

CPC classification number: G09G3/18 ,  G06F3/0412 ,  G06F3/044 ,  G09G3/3611 ,  G09G3/3696 ,  G09G2310/0278 ,  G09G2330/02 ,  G09G2330/022

Abstract: An LCD controller includes a charge pump circuit for generating a charge voltage responsive to an external voltage and a clock signal. An oscillator generates the clock signal responsive to at least one bias voltage. The oscillator has a high power mode of operation and a low power mode of operation. Bias circuitry for applies the at least one bias voltage to the oscillator. The at least one bias voltage is applied to the oscillator from an external source in the high power mode of operation and the at least one bias voltage is applied to the oscillator from a source within the oscillator in the low power mode of operation. An LCD driver voltage circuit generates a plurality of LCD driver voltages for driving segments of an LCD display responsive to the charge voltage.

Abstract translation: LCD控制器包括用于产生响应于外部电压和时钟信号的充电电压的电荷泵电路。 振荡器响应于至少一个偏置电压产生时钟信号。 振荡器具有高功率工作模式和低功耗工作模式。 用于将至少一个偏置电压施加到振荡器的偏置电路。 在高功率工作模式下，至少一个偏置电压从外部源施加到振荡器，并且至少一个偏置电压在低功耗工作模式下从振荡器内的源施加到振荡器。 LCD驱动器电压电路响应于充电电压产生用于驱动LCD显示器段的多个LCD驱动器电压。

公开(公告)号：US20100079439A1

公开(公告)日：2010-04-01

申请号：US12241800

申请日：2008-09-30

Applicant: FARRIS BAR ,  GOLAM R. CHOWDHURY ,  DOUGLAS PIASECKI ,  THOMAS S. DAVID

Inventor： FARRIS BAR ,  GOLAM R. CHOWDHURY ,  DOUGLAS PIASECKI ,  THOMAS S. DAVID

IPC: G06F3/038

CPC classification number: G09G3/3696 ,  G09G3/04 ,  G09G2330/021

Abstract: Charge pump circuitry comprises a voltage for generating a first regulated voltage. A low drop out regulator generates a second regulated voltage responsive to the first regulated voltage. A charge pump voltage generation circuit generates a voltage. First and second resistor strings are responsive to the generated voltage. The first resistor string provides a first plurality of bias voltages to an LCD responsive to the voltage in a first mode of operation and the second resistor string provides faster charging and discharging of the connected LCD elements responsive to a second mode of operation.

Abstract translation: 电荷泵电路包括用于产生第一调节电压的电压。 低压降稳压器响应于第一调节电压产生第二调节电压。 电荷泵电压产生电路产生电压。 第一和第二电阻器串响应于所产生的电压。 第一电阻器串响应于第一操作模式中的电压而向LCD提供第一多个偏压，并且响应于第二操作模式，第二电阻串提供连接的LCD元件的更快的充电和放电。

公开(公告)号：US20050204224A1

公开(公告)日：2005-09-15

申请号：US11114840

申请日：2005-04-26

Applicant: Douglas Piasecki ,  Alvin Storvik

Inventor： Douglas Piasecki ,  Alvin Storvik

IPC: G01R31/28 ,  G06F7/38 ,  G06F13/40 ,  H03K19/173

CPC classification number: G06F13/4072

Abstract: A pin interface for an integrated circuit. The pin interface includes logic gates for processing digital signals, and analog lines for carrying analog signals. The pin interface includes circuits for disabling the digital circuits when configured to carry analog signals. A comparator is associated with at least one of the pins for comparing the analog voltage level thereon with a reference voltage.

Abstract translation: 集成电路的引脚接口。 引脚接口包括用于处理数字信号的逻辑门和用于承载模拟信号的模拟线。 引脚接口包括用于在配置为承载模拟信号时禁用数字电路的电路。 比较器与至少一个引脚相关联，用于将其上的模拟电压电平与参考电压进行比较。

公开(公告)号：US20110157140A1

公开(公告)日：2011-06-30

申请号：US12651311

申请日：2009-12-31

Applicant: DOUGLAS PIASECKI ,  THOMAS S. DAVID ,  TIMOTHY THOMAS RUEGER ,  STEFAN MASTOVICH ,  JIA-HAU LIU

Inventor： DOUGLAS PIASECKI ,  THOMAS S. DAVID ,  TIMOTHY THOMAS RUEGER ,  STEFAN MASTOVICH ,  JIA-HAU LIU

IPC: G09G5/00

CPC classification number: G06F3/0416 ,  G06F3/044 ,  G09G3/18 ,  G09G3/3681 ,  G09G3/3692 ,  G09G3/3696 ,  G09G2310/0278 ,  G09G2310/08 ,  G09G2320/0606 ,  G09G2320/066 ,  G09G2330/025

Abstract: An output pad control logic comprises an output buffer including a plurality of transistors connected to drive signals for an output pad. Each of the plurality of transistors includes an n-well. An n-well generator connects a first voltage to the n-wells of the plurality of transistors of the output buffer in a first mode of operation when a system rail voltage exceeds a pad voltage applied to the output pad. The n-well generator connects the pad voltage to the n-wells of the plurality of transistors of the output buffer in a second mode of operation when the pad voltage applied to the output buffer exceeds the system rail voltage. A switching circuit is responsive to at least one control signal to connect the system rail voltage as the first voltage when the output pad is not driving an LCD display and to connect a larger of the system rail voltage and an LCD drive voltage as the first voltage when the output pad is driving the LCD display.

Abstract translation: 输出焊盘控制逻辑包括输出缓冲器，其包括连接到用于输出焊盘的驱动信号的多个晶体管。 多个晶体管中的每一个包括n阱。 当系统轨道电压超过施加到输出焊盘的焊盘电压时，n阱发生器以第一操作模式将第一电压连接到输出缓冲器的多个晶体管的n阱。 当施加到输出缓冲器的焊盘电压超过系统轨道电压时，n阱发生器以第二操作模式将焊盘电压连接到输出缓冲器的多个晶体管的n阱。 当输出焊盘不驱动LCD显示器时，切换电路响应于至少一个控制信号来连接系统轨电压作为第一电压，并且将较大的系统轨电压和LCD驱动电压连接为第一电压 当输出板正在驱动LCD显示屏时。