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    METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING VERTICAL CHANNELS AND SEMICONDUCTOR DEVICES FORMED USING SUCH METHODS
    1.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING VERTICAL CHANNELS AND SEMICONDUCTOR DEVICES FORMED USING SUCH METHODS 有权
    形成包括垂直通道的半导体器件的方法和使用这种方法形成的半导体器件

    公开(公告)号：US20150064885A1

    公开(公告)日：2015-03-05

    申请号：US14309018

    申请日：2014-06-19

    申请人： Bo-Young Lee ,  Jong-Wan Choi ,  Dae-Hun Choi ,  Myoung-Bum Lee

    发明人： Bo-Young Lee ,  Jong-Wan Choi ,  Dae-Hun Choi ,  Myoung-Bum Lee

    IPC分类号： H01L27/115 ,  H01L21/02 ,  H01L21/28

    CPC分类号： H01L27/11556 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7827

    摘要： Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods are provided. The methods may include forming a stack including a plurality of insulating patterns alternating with a plurality of conductive patterns on an upper surface of a substrate and forming a hole through the stack. The hole may expose sidewalls of the plurality of insulating patterns and the plurality of conductive patterns. The sidewalls of the plurality of insulating patterns may be aligned along a first plane that is slanted with respect to the upper surface of the substrate, and midpoints of the respective sidewalls of the plurality of conductive patterns may be aligned along a second plane that is substantially perpendicular to the upper surface of the substrate.

    摘要翻译： 提供了使用这种方法形成的包括垂直沟道和半导体器件的半导体器件的形成方法。 所述方法可以包括形成堆叠，其包括与衬底的上表面上的多个导电图案交替的多个绝缘图案，并且通过堆叠形成孔。 孔可以暴露多个绝缘图案和多个导电图案的侧壁。 多个绝缘图案的侧壁可以沿着相对于衬底的上表面倾斜的第一平面对齐，并且多个导电图案的相应侧壁的中点可以沿着基本上 垂直于衬底的上表面。

    Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods
    2.
    发明授权
    Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods 有权
    形成半导体器件的方法包括使用这种方法形成的垂直沟道和半导体器件

    公开(公告)号：US09040378B2

    公开(公告)日：2015-05-26

    申请号：US14309018

    申请日：2014-06-19

    申请人： Bo-Young Lee ,  Jong-Wan Choi ,  Dae-Hun Choi ,  Myoung-Bum Lee

    发明人： Bo-Young Lee ,  Jong-Wan Choi ,  Dae-Hun Choi ,  Myoung-Bum Lee

    IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L21/28 ,  H01L21/02

    CPC分类号： H01L27/11556 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7827

    摘要： Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods are provided. The methods may include forming a stack including a plurality of insulating patterns alternating with a plurality of conductive patterns on an upper surface of a substrate and forming a hole through the stack. The hole may expose sidewalls of the plurality of insulating patterns and the plurality of conductive patterns. The sidewalls of the plurality of insulating patterns may be aligned along a first plane that is slanted with respect to the upper surface of the substrate, and midpoints of the respective sidewalls of the plurality of conductive patterns may be aligned along a second plane that is substantially perpendicular to the upper surface of the substrate.

    摘要翻译： 提供了使用这种方法形成的包括垂直沟道和半导体器件的半导体器件的形成方法。 所述方法可以包括形成堆叠，其包括与衬底的上表面上的多个导电图案交替的多个绝缘图案，并且通过堆叠形成孔。 孔可以暴露多个绝缘图案和多个导电图案的侧壁。 多个绝缘图案的侧壁可以沿着相对于衬底的上表面倾斜的第一平面对齐，并且多个导电图案的相应侧壁的中点可以沿着基本上 垂直于衬底的上表面。

    METHOD OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICES
    3.
    发明申请
    METHOD OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICES 审中-公开
    制造垂直半导体器件的方法

    公开(公告)号：US20110306195A1

    公开(公告)日：2011-12-15

    申请号：US13099485

    申请日：2011-05-03

    申请人： Jin-Gyun Kim ,  Bo-Young Lee ,  Ki-Hyun Hwang ,  Eunkee Hong ,  Jong-Wan Choi

    发明人： Jin-Gyun Kim ,  Bo-Young Lee ,  Ki-Hyun Hwang ,  Eunkee Hong ,  Jong-Wan Choi

    IPC分类号： H01L21/28

    CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

    摘要： In a vertical semiconductor device and a method of manufacturing a vertical semiconductor device, sacrificial layers and insulating interlayers are repeatedly and alternately stacked on a substrate. The sacrificial layers include boron (B) and nitrogen (N) and have an etching selectivity with respect to the insulating interlayers. Semiconductor patterns are formed on the substrate through the sacrificial layers and the insulating interlayers. The sacrificial layers and the insulating interlayers are at least partially removed between the semiconductor patterns to form sacrificial layer patterns and insulating interlayer patterns on sidewalls of the semiconductor patterns. The sacrificial layer patterns are removed to form grooves between the insulating interlayer patterns. The grooves expose portions of the sidewalls of the semiconductor patterns. A gate structure is formed in each of the grooves.

    摘要翻译： 在垂直半导体器件和制造垂直半导体器件的方法中，牺牲层和绝缘夹层重叠交替堆叠在衬底上。 牺牲层包括硼（B）和氮（N），并且相对于绝缘夹层具有蚀刻选择性。 通过牺牲层和绝缘夹层在衬底上形成半导体图案。 在半导体图案之间至少部分去除牺牲层和绝缘夹层，以在半导体图案的侧壁上形成牺牲层图案和绝缘层间图案。 去除牺牲层图案以在绝缘层间图案之间形成凹槽。 凹槽暴露半导体图案的侧壁的部分。 在每个槽中形成栅极结构。

    SEMICONDUCTOR DEVICES WITH AN AIR GAP IN TRENCH ISOLATION DIELECTRIC
    4.
    发明申请
    SEMICONDUCTOR DEVICES WITH AN AIR GAP IN TRENCH ISOLATION DIELECTRIC 审中-公开
    具有气隙隔离绝缘电介质的半导体器件

    公开(公告)号：US20100230741A1

    公开(公告)日：2010-09-16

    申请号：US12711033

    申请日：2010-02-23

    申请人： Jongwan Choi ,  Eunkee Hong ,  Bo-Young Lee ,  Tae-Jong Han ,  Juseon Goo ,  Kyungmun Byun

    发明人： Jongwan Choi ,  Eunkee Hong ,  Bo-Young Lee ,  Tae-Jong Han ,  Juseon Goo ,  Kyungmun Byun

    IPC分类号： H01L29/792 ,  H01L29/06

    CPC分类号： H01L29/7881 ,  H01L21/76229 ,  H01L21/764 ,  H01L27/11521 ,  H01L27/11531 ,  H01L27/11568 ,  H01L29/0649

    摘要： A tunnel insulating layer and a charge storage layer are sequentially stacked on a substrate. A recess region penetrates the charge storage layer, the tunnel insulating layer and a portion of the substrate. The recess region is defined by a bottom surface and a side surface extending from the bottom surface. A first dielectric pattern includes a bottom portion covering the bottom surface and inner walls extending from the bottom portion and covering a portion of the side surface of the recess region. A second dielectric pattern is in the recess region between the inner walls of the first dielectric pattern, and the second dielectric pattern enclosing an air gap. The air gap that is enclosed by the second dielectric pattern may extend through a major portion of the second dielectric pattern in a direction away from the bottom surface of the recess region.

    摘要翻译： 隧道绝缘层和电荷存储层依次层叠在基板上。 凹陷区域穿透电荷存储层，隧道绝缘层和基底的一部分。 凹陷区域由底表面和从底表面延伸的侧表面限定。 第一电介质图案包括覆盖底面的底部和从底部延伸并覆盖凹部区域的侧表面的一部分的内壁。 第二电介质图案位于第一电介质图案的内壁之间的凹陷区域中，并且第二电介质图案包围气隙。 由第二电介质图案包围的空气间隙可以沿着远离凹部区域的底表面的方向延伸穿过第二电介质图案的主要部分。

    Apparatus for forming thermal fatigue cracks
    6.
    发明授权
    Apparatus for forming thermal fatigue cracks 失效
    用于形成热疲劳裂纹的装置

    公开(公告)号：US07559251B2

    公开(公告)日：2009-07-14

    申请号：US11625706

    申请日：2007-01-22

    申请人： Bo-Young Lee ,  Duck Hee Ryu ,  Jae Seong Kim ,  Yong Kim ,  Dae Hwan An

    发明人： Bo-Young Lee ,  Duck Hee Ryu ,  Jae Seong Kim ,  Yong Kim ,  Dae Hwan An

    IPC分类号： G01N3/32

    CPC分类号： G01N3/60 ,  G01N2203/0066 ,  G01N2203/0073 ,  G01N2203/027

    摘要： Disclosed is an apparatus and method for forming thermal fatigue cracks in a test piece for performance demonstration of nondestructive testing. The apparatus for forming thermal fatigue cracks includes a heating unit, having a conductive member attached around the outer surface of a pipe test piece and an induction heating coil disposed adjacent to the conductive member; a cooling unit, having a cooling water pump for forcibly supplying cooling water to the inner surface of the pipe test piece from a cooling water storage source and a cooling water hose; and a control unit for controlling operation of the heating unit and the cooling unit. Accordingly, thermal fatigue cracks similar to actual thermal fatigue cracks occurring during the operation of nuclear power plants or processing industry equipment are formed in a test piece, thereby assuring effective performance demonstration of nondestructive testing.

    摘要翻译： 公开了一种用于在无损检测的性能演示中形成试验片中的热疲劳裂纹的装置和方法。 用于形成热疲劳裂纹的装置包括加热单元，其具有附接在管道试件的外表面上的导电构件和邻近导电构件设置的感应加热线圈; 冷却单元，具有冷却水泵，用于从冷却水存储源和冷却水软管向管道试件的内表面强制供给冷却水; 以及用于控制加热单元和冷却单元的操作的控制单元。 因此，在试验片中形成类似于在核电厂或加工工业设备运行期间发生的实际热疲劳裂纹的热疲劳裂纹，从而确保了非破坏性试验的有效性能演示。

    Oil recovery system
    9.
    发明授权
    Oil recovery system 失效
    油回收系统

    公开(公告)号：US06592753B2

    公开(公告)日：2003-07-15

    申请号：US10117646

    申请日：2002-04-05

    申请人： Bo-Young Lee

    发明人： Bo-Young Lee

    IPC分类号： C02F140

    CPC分类号： B01D17/0208 ,  B01D17/0211 ,  B01D17/0214 ,  Y10S210/923

    摘要： An oil recovery system, designed to recover oil from oil-contaminated water of a river, lake or sea due to a difference in specific gravity of the liquids. The system includes a 4-stage separation tank 15 having four chambers 51-54. The first chamber 51 includes a hopper-shaped oil floating unit 59 in communication with a piston pump 68 (FIG. 5) and having porous filters 61, 62 therein. The second and third chambers 52, 53 include a plurality of horizontal diaphragms 63 for reducing the processing time for separating oil from water. The system can be continuously operated without being stopped during an oil recovering operation. The oil recovered from discharged pipe 67 is usable so that the system preferably conserves natural resources.

    摘要翻译： 一种采油系统，用于由于液体比重差异，从河流，湖泊或海洋的油污水中回收油。 该系统包括具有四个室51-54的四级分离槽15。 第一室51包括与活塞泵68（图5）连通并且其中具有多孔过滤器61,62的料斗形状的油浮动单元59。 第二和第三室52,53包括多个水平隔膜63，用于减少从水中分离油的处理时间。 在油回收操作期间，系统可以连续运行而不停止。 从排出管67回收的油可以使用，使得该系统优选地保存自然资源。