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1.发明授权Circuits and methods for placing programmable impedance memory elements in high impedance states 有权将可编程阻抗存储器元件置于高阻态中的电路和方法公开(公告)号：US08730752B1
公开(公告)日：2014-05-20
申请号：US13437906
申请日：2012-04-02
IPC分类号： G11C5/14
CPC分类号： G11C13/0011 , G11C13/0038 , G11C13/0069 , G11C13/0097 , G11C2013/0073
摘要： A memory device can include a load circuit coupled in series with at least one memory element between two nodes and configured to enable a programming current to flow through the memory element to lower its impedance, and configured to enable an erase current to flow through the element in a direction opposite to the program current, the erase current varying in response to an erase voltage applied across the two nodes as the memory element impedance increases.
摘要翻译： 存储器件可以包括负载电路，其与两个节点之间的至少一个存储器元件串联耦合，并且被配置为使得编程电流能够流过存储器元件以降低其阻抗，并且被配置为使得擦除电流能够流过元件 在与编程电流相反的方向上，当存储元件阻抗增加时，擦除电流响应于施加在两个节点上的擦除电压而变化。
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2.发明授权Circuits and methods for placing programmable impedance memory elements in high impedance states 有权将可编程阻抗存储器元件置于高阻态中的电路和方法公开(公告)号：US09368198B1
公开(公告)日：2016-06-14
申请号：US14281830
申请日：2014-05-19
CPC分类号： G11C13/0011 , G11C13/0038 , G11C13/0069 , G11C13/0097 , G11C2013/0073
摘要： A memory device can include a plurality of two terminal conductive bridging random access memory (CBRAM) type memory elements; at least one program transistor configured to enable a program current to flow through at least one memory element in response to the application of a program signal at its control terminal and a program bias voltage to the memory element; and an erase load circuit that includes at least one two-terminal diode-like load element, the erase load circuit configured to enable an erase current to flow through the load element and at least one memory element in a direction opposite to that of the program current.
摘要翻译： 存储器件可以包括多个两端导电桥接随机存取存储器（CBRAM）型存储器元件; 至少一个程序晶体管被配置为响应于在其控制端处应用程序信号而使程序电流流过至少一个存储器元件，并且将程序偏置电压提供给存储器元件; 以及擦除负载电路，其包括至少一个二端二极管状负载元件，所述擦除负载电路被配置为使得擦除电流能够以与所述程序相反的方向流过所述负载元件和至少一个存储元件 当前。
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公开(公告)号：US09029829B1
公开(公告)日：2015-05-12
申请号：US13462659
申请日：2012-05-02
CPC分类号： H01L27/2463 , G11C5/06 , G11C11/005 , G11C11/56 , G11C11/5614 , G11C13/0002 , G11C13/0011 , G11C13/003 , G11C13/0069 , G11C17/16 , G11C17/165 , G11C29/74 , G11C2013/0073 , G11C2213/52 , G11C2213/78 , G11C2213/79 , G11C2213/82
摘要： A memory cell includes a first resistive switching device having a first terminal and a second terminal, a switching device having a first terminal and a second terminal, and an access device having a first access terminal and a second access terminal. The first access terminal is coupled to the first terminal of the first resistive switching device and the first terminal of the switching device.
摘要翻译： 存储单元包括具有第一端子和第二端子的第一电阻式开关器件，具有第一端子和第二端子的开关器件以及具有第一接入端子和第二接入端子的接入设备。 第一接入终端耦合到第一电阻式交换设备的第一终端和交换设备的第一终端。
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4.发明授权Method of operating a resistive memory device with a ramp-up/ramp-down program/erase pulse 有权使用斜坡上升/斜坡下降程序/擦除脉冲操作电阻式存储器件的方法公开(公告)号：US09165644B2
公开(公告)日：2015-10-20
申请号：US13470030
申请日：2012-05-11
申请人： Deepak Kamalanathan , Foroozan Sarah Koushan , Juan Pablo Saenz Echeverry , John Dinh , Shane C. Hollmer , Michael Kozicki
发明人： Deepak Kamalanathan , Foroozan Sarah Koushan , Juan Pablo Saenz Echeverry , John Dinh , Shane C. Hollmer , Michael Kozicki
IPC分类号： G11C13/00
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2013/0092 , G11C2213/79
摘要： In one embodiment, a method of operating a resistive switching device includes applying a signal comprising a pulse on a first terminal of a two terminal resistive switching device having the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period. The first time period is at least 0.1 times a total time period of the pulse.
摘要翻译： 在一个实施例中，一种操作电阻式开关装置的方法包括在具有第一端子和第二端子的二端电阻式开关装置的第一端上施加包括脉冲的信号。 电阻式开关装置具有第一状态和第二状态。 脉冲包括在第一时间段内从第一电压到第二电压的第一斜坡。 第一时间段是脉冲总时间的至少0.1倍。
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公开(公告)号：US20130301337A1
公开(公告)日：2013-11-14
申请号：US13470030
申请日：2012-05-11
申请人： Deepak Kamalanathan , Foroozan Sarah Koushan , Juan Pablo Saenz Echeverry , John Dinh , Shane C. Hollmer , Michael Kozicki
发明人： Deepak Kamalanathan , Foroozan Sarah Koushan , Juan Pablo Saenz Echeverry , John Dinh , Shane C. Hollmer , Michael Kozicki
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2013/0092 , G11C2213/79
摘要： In one embodiment, a method of operating a resistive switching device includes applying a signal comprising a pulse on a first terminal of a two terminal resistive switching device having the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period. The first time period is at least 0.1 times a total time period of the pulse.
摘要翻译： 在一个实施例中，一种操作电阻式开关装置的方法包括在具有第一端子和第二端子的二端电阻式开关装置的第一端上施加包括脉冲的信号。 电阻式开关装置具有第一状态和第二状态。 脉冲包括在第一时间段内从第一电压到第二电压的第一斜坡。 第一时间段是脉冲总时间的至少0.1倍。
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