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172 条记录 (耗时 0.024 秒)

    Memory cell arrangement
    1.
    发明授权
    Memory cell arrangement 失效
    存储单元布置

    公开(公告)号：US06627940B1

    公开(公告)日：2003-09-30

    申请号：US09937838

    申请日：2002-02-05

    申请人： Dirk Schumann ,  Bernhard Sell ,  Hans Reisinger ,  Josef Willer

    发明人： Dirk Schumann ,  Bernhard Sell ,  Hans Reisinger ,  Josef Willer

    IPC分类号： H01L27108

    CPC分类号： H01L27/10876 ,  H01L27/10808 ,  H01L27/10823

    摘要： A memory-cell array includes a substrate forming parallel first and second trenches. A transistor's upper source/drain region adjoins two of the first and two of the second trenches, and lies above its lower source/drain region. A conductive structure in a first trench associated with the transistor adjoins the upper source/drain region at its first edge. An insulating structure in the associated first trench insulates the conductive structure from a second edge and from a bottom of the associated first trench. A word line, on which is a further insulating layer, is over the upper/source drain region and parallel to the associated first trench bulges into the second trenches. Insulating spaces adjoin the word line laterally. A contact on the conductive structure and in electrical communication with the upper source/drain region connects with a capacitor.

    摘要翻译： 存储单元阵列包括形成平行的第一和第二沟槽的衬底。 晶体管的上部源极/漏极区域邻接第一和第二个第二沟槽中的两个，并且位于其下部源极/漏极区域的上方。 与晶体管相关联的第一沟槽中的导电结构在其第一边缘邻接上部源极/漏极区。 相关联的第一沟槽中的绝缘结构将导电结构与相关联的第一沟槽的第二边缘和底部绝缘。 在其上是另一个绝缘层的字线在上部/源极漏极区域上方并且平行于相关联的第一沟槽凸起进入第二沟槽。 绝缘空间横向与字线连接。 导电结构上的与上部源极/漏极区域电连通的触点与电容器连接。

    Integrated circuit configuration with at least one capacitor and method for producing the same
    2.
    发明授权
    Integrated circuit configuration with at least one capacitor and method for producing the same 有权
    具有至少一个电容器的集成电路配置及其制造方法

    公开(公告)号：US06525363B1

    公开(公告)日：2003-02-25

    申请号：US09677433

    申请日：2000-10-02

    申请人： Josef Willer ,  Bernhard Sell ,  Dirk Schumann

    发明人： Josef Willer ,  Bernhard Sell ,  Dirk Schumann

    IPC分类号： H01L27108

    CPC分类号： H01L28/84 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10885 ,  H01L28/86 ,  H01L28/90

    摘要： A first capacitor electrode of the capacitor, which is arranged on a surface of a substrate (1), has a lower part (T) and a lateral part (S) arranged thereon. At least a first lateral area of the lateral part (S) is undulatory in such a way that it has bulges and indentations alternately which are formed along lines each running in a plane parallel to the surface of the substrate (1). The lateral part (T) can be produced by depositing conductive material in a depression (V) which is produced in a layer sequence whose layers are composed alternately of a first material and a second material and in which the first material is subjected to wet etching selectively with respect to the second material down to a first depth. The first capacitor electrode is provided with a capacitor dielectric (KD). A second capacitor electrode (P) adjoins the capacitor dielectric (KD).

    摘要翻译： 设置在基板（1）的表面上的电容器的第一电容电极具有布置在其上的下部（T）和侧部（S）。 横向部分（S）的至少第一横向区域以这样的方式波动，使得其具有沿着平行于基底（1）的表面的平面中的每条线条沿着线形成的凸起和凹陷。 横向部分（T）可以通过将导电材料沉积在层中产生的凹陷（V）中来制造，层的顺序是层，其层由第一材料和第二材料交替组成，并且其中第一材料经受湿蚀刻 相对于第二材料选择性地到达第一深度。 第一电容器电极设置有电容器电介质（KD）。 第二电容器电极（P）与电容器电介质（KD）相邻。

    DRAM cell configuration and fabrication method
    4.
    发明授权
    DRAM cell configuration and fabrication method 有权

    公开(公告)号：US06504200B2

    公开(公告)日：2003-01-07

    申请号：US09951243

    申请日：2001-09-12

    申请人： Till Schlösser ,  Bernhard Sell ,  Josef Willer

    发明人： Till Schlösser ,  Bernhard Sell ,  Josef Willer

    IPC分类号： H01L27108

    CPC分类号： H01L27/10876 ,  H01L27/10808 ,  H01L27/10823

    摘要： Bit lines are arranged in the lower parts of trenches of a substrate. Word lines are located above the substrate except for protuberances or bulges, which extend downwards into the trenches and which are arranged above the bit lines. The transistors are vertical transistors whose source/drain regions are located below the word lines and between adjacent trenches. The capacitors are linked with the upper source/drain regions. Conductive structures that surround the word lines from the top and the sides while being insulated from the word lines and bordering on the upper source/drain regions can link the upper source/drain regions with the capacitors.

    Integrated circuit configuration and method of fabricating a dram structure with buried bit lines or trench capacitors
    5.
    发明授权
    Integrated circuit configuration and method of fabricating a dram structure with buried bit lines or trench capacitors 失效
    集成电路结构和制造具有掩埋位线或沟槽电容器的电容结构的方法

    公开(公告)号：US06800898B2

    公开(公告)日：2004-10-05

    申请号：US09951239

    申请日：2001-09-12

    申请人： Annalisa Cappelani ,  Bernhard Sell ,  Josef Willer

    发明人： Annalisa Cappelani ,  Bernhard Sell ,  Josef Willer

    IPC分类号： H01L2976

    CPC分类号： H01L27/10844 ,  H01L27/10861 ,  H01L27/10876

    摘要： The bottom and the sides of a lower part of recess formed in the substrate has an insulating structure. A first part of the conductive structure of a first electric conductivity type is located in the lower part of the recess. A second part of the conductive structure of a second electric conductivity type, lower than the first type, is located in an upper part and borders the region of the substrate at the sides of the recess. The conductive structure has a diffusion barrier between its first and second parts. The conductive structure is configured as a bit line of a DRAM cell configuration with a vertical transistor, whereby S/Du represents the lower source/drain area and S/Do represents the upper source/drain area connected to a memory capacitor. Or, the conductive structure is configured as a memory capacitor and the upper source drain/area is connected to a bit line.

    摘要翻译： 形成在基板中的凹部的下部的底部和侧面具有绝缘结构。 第一导电类型的导电结构的第一部分位于凹部的下部。 低于第一类型的第二导电类型的导电结构的第二部分位于上部并且在凹部的侧面与基板的区域相邻。 导电结构在其第一和第二部分之间具有扩散阻挡层。 导电结构被配置为具有垂直晶体管的DRAM单元配置的位线，由此S / Du表示下源极/漏极区域，S / Do表示连接到存储电容器的上部源极/漏极区域。 或者，导电结构被配置为存储电容器，并且上部源极漏极/区域连接到位线。

    Integrated circuit having a base structure and a nanostructure
    9.
    发明申请
    Integrated circuit having a base structure and a nanostructure 审中-公开
    具有基底结构和纳米结构的集成电路

    公开(公告)号：US20090251968A1

    公开(公告)日：2009-10-08

    申请号：US12099522

    申请日：2008-04-08

    申请人： Christoph Andreas Kleint ,  Josef Willer

    发明人： Christoph Andreas Kleint ,  Josef Willer

    IPC分类号： H01L21/00 ,  G11C16/04

    CPC分类号： H01L27/11578 ,  H01L27/11582

    摘要： In an embodiment, an integrated circuit may include a metallically conductive structure, a base structure having a crystal orientation, the base structure being adjacent to the metallically conductive structure, and a nanostructure disposed on the base structure, the nanostructure having substantially the same crystal orientation as the base structure.

    摘要翻译： 在一个实施例中，集成电路可以包括金属导电结构，具有晶体取向的基底结构，与金属导电结构相邻的基底结构，以及设置在基底结构上的纳米结构，纳米结构具有基本上相同的晶体取向 作为基础结构。