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25 条记录 (耗时 0.021 秒)

    Trench capacitor and method for fabricating the trench capacitor
    1.
    发明授权
    Trench capacitor and method for fabricating the trench capacitor 失效
    沟槽电容器和制造沟槽电容器的方法

    公开(公告)号：US06987295B2

    公开(公告)日：2006-01-17

    申请号：US10650817

    申请日：2003-08-28

    申请人： Bernhard Sell ,  Annette Sänger ,  Dirk Schumann

    发明人： Bernhard Sell ,  Annette Sänger ,  Dirk Schumann

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10861 ,  H01L27/1203

    摘要： A trench capacitor for use in a DRAM memory cell contains a lower capacitor electrode, a storage dielectric, and an upper capacitor electrode, which are at least partially disposed in a trench. The lower capacitor electrode adjoins, in a lower trench region, a wall of the trench, while in the upper trench region there is a spacer layer that adjoins a wall of the trench and is made from an insulating material. The upper electrode contains at least three layers, a first layer disposed in the trench on the storage dielectric and containing doped polysilicon, a second layer disposed on the first layer and containing metal-silicide, and a third layer disposed on the second layer and containing doped polysilicon. The layers of the upper electrode in each case extending along the walls and the base of the trench up to at least the upper edge of the spacer layer.

    摘要翻译： 用于DRAM存储单元的沟槽电容器包括至少部分地设置在沟槽中的下电容器电极，存储电介质和上电容器电极。 下部电容器电极在下部沟槽区域中邻接沟槽的壁，而在上部沟槽区域中存在间隔层，该间隔层邻接沟槽的壁并由绝缘材料制成。 上电极包含至少三层，第一层设置在存储电介质上的沟槽中并含有掺杂多晶硅，第二层设置在第一层上并含有金属硅化物，第三层设置在第二层上并含有 掺杂多晶硅。 每个壳体中的上电极的层沿着沟槽的壁和基底延伸到至少间隔层的上边缘。

    Method for fabricating a storage capacitor
    3.
    发明申请
    Method for fabricating a storage capacitor 审中-公开
    存储电容器的制造方法

    公开(公告)号：US20060073659A1

    公开(公告)日：2006-04-06

    申请号：US11285639

    申请日：2005-11-22

    申请人： Bernhard Sell ,  Annette Sanger ,  Dirk Schumann

    发明人： Bernhard Sell ,  Annette Sanger ,  Dirk Schumann

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10861 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/28518 ,  H01L21/31604 ,  H01L27/10814 ,  H01L28/60

    摘要： The present invention relates to a novel method for fabricating a storage capacitor designed as a trench or a stacked capacitor and is used in particular in a DRAM memory cell. The method includes steps of forming a lower, metallic capacitor electrode, a storage dielectric and an upper capacitor electrode. The lower, metallic capacitor electrode is formed in a self-aligned manner on a silicon base material in such a way that uncovered silicon regions are first produced at locations at which the lower capacitor electrode will be formed, and then metal silicide is selectively formed on the uncovered silicon regions.

    摘要翻译： 本发明涉及一种用于制造设计为沟槽或层叠电容器的存储电容器的新颖方法，特别用于DRAM存储单元。 该方法包括形成下部金属电容器电极，存储电介质和上部电容器电极的步骤。 下部金属电容器电极以自对准的方式形成在硅基材上，使得首先在将形成下电容器电极的位置处产生未覆盖的硅区域，然后选择性地形成金属硅化物 未覆盖的硅区域。

    Memory cell arrangement
    5.
    发明授权
    Memory cell arrangement 失效
    存储单元布置

    公开(公告)号：US06627940B1

    公开(公告)日：2003-09-30

    申请号：US09937838

    申请日：2002-02-05

    申请人： Dirk Schumann ,  Bernhard Sell ,  Hans Reisinger ,  Josef Willer

    发明人： Dirk Schumann ,  Bernhard Sell ,  Hans Reisinger ,  Josef Willer

    IPC分类号： H01L27108

    CPC分类号： H01L27/10876 ,  H01L27/10808 ,  H01L27/10823

    摘要： A memory-cell array includes a substrate forming parallel first and second trenches. A transistor's upper source/drain region adjoins two of the first and two of the second trenches, and lies above its lower source/drain region. A conductive structure in a first trench associated with the transistor adjoins the upper source/drain region at its first edge. An insulating structure in the associated first trench insulates the conductive structure from a second edge and from a bottom of the associated first trench. A word line, on which is a further insulating layer, is over the upper/source drain region and parallel to the associated first trench bulges into the second trenches. Insulating spaces adjoin the word line laterally. A contact on the conductive structure and in electrical communication with the upper source/drain region connects with a capacitor.

    摘要翻译： 存储单元阵列包括形成平行的第一和第二沟槽的衬底。 晶体管的上部源极/漏极区域邻接第一和第二个第二沟槽中的两个，并且位于其下部源极/漏极区域的上方。 与晶体管相关联的第一沟槽中的导电结构在其第一边缘邻接上部源极/漏极区。 相关联的第一沟槽中的绝缘结构将导电结构与相关联的第一沟槽的第二边缘和底部绝缘。 在其上是另一个绝缘层的字线在上部/源极漏极区域上方并且平行于相关联的第一沟槽凸起进入第二沟槽。 绝缘空间横向与字线连接。 导电结构上的与上部源极/漏极区域电连通的触点与电容器连接。

    Integrated circuit configuration with at least one capacitor and method for producing the same
    7.
    发明授权
    Integrated circuit configuration with at least one capacitor and method for producing the same 有权
    具有至少一个电容器的集成电路配置及其制造方法

    公开(公告)号：US06525363B1

    公开(公告)日：2003-02-25

    申请号：US09677433

    申请日：2000-10-02

    申请人： Josef Willer ,  Bernhard Sell ,  Dirk Schumann

    发明人： Josef Willer ,  Bernhard Sell ,  Dirk Schumann

    IPC分类号： H01L27108

    CPC分类号： H01L28/84 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10885 ,  H01L28/86 ,  H01L28/90

    摘要： A first capacitor electrode of the capacitor, which is arranged on a surface of a substrate (1), has a lower part (T) and a lateral part (S) arranged thereon. At least a first lateral area of the lateral part (S) is undulatory in such a way that it has bulges and indentations alternately which are formed along lines each running in a plane parallel to the surface of the substrate (1). The lateral part (T) can be produced by depositing conductive material in a depression (V) which is produced in a layer sequence whose layers are composed alternately of a first material and a second material and in which the first material is subjected to wet etching selectively with respect to the second material down to a first depth. The first capacitor electrode is provided with a capacitor dielectric (KD). A second capacitor electrode (P) adjoins the capacitor dielectric (KD).

    摘要翻译： 设置在基板（1）的表面上的电容器的第一电容电极具有布置在其上的下部（T）和侧部（S）。 横向部分（S）的至少第一横向区域以这样的方式波动，使得其具有沿着平行于基底（1）的表面的平面中的每条线条沿着线形成的凸起和凹陷。 横向部分（T）可以通过将导电材料沉积在层中产生的凹陷（V）中来制造，层的顺序是层，其层由第一材料和第二材料交替组成，并且其中第一材料经受湿蚀刻 相对于第二材料选择性地到达第一深度。 第一电容器电极设置有电容器电介质（KD）。 第二电容器电极（P）与电容器电介质（KD）相邻。

    Method and composition for cleaning objects
    8.
    发明授权
    Method and composition for cleaning objects 有权
    清洁物品的方法和组成

    公开(公告)号：US08834643B2

    公开(公告)日：2014-09-16

    申请号：US13259536

    申请日：2010-03-22

    申请人： Dirk Schumann ,  Rainer Surkow

    发明人： Dirk Schumann ,  Rainer Surkow

    IPC分类号： B08B3/04 ,  C11D3/18 ,  C11D3/20 ,  C11D17/00 ,  C11D3/00 ,  C11D3/32 ,  C11D1/825 ,  C11D1/83

    CPC分类号： C11D17/0021 ,  C11D1/825 ,  C11D1/83 ,  C11D3/0052 ,  C11D3/18 ,  C11D3/20 ,  C11D3/201 ,  C11D3/2041 ,  C11D3/2072 ,  C11D3/2093 ,  C11D3/32

    摘要： A method for cleaning objects made of organic or inorganic materials, wherein the relevant material is brought into contact with a composition in the form of a fluid nanophase system, comprising a) at least one water-insoluble substance having a water solubility of less than 4 grams per liter, b) at least one amphiphilic substance (NP-MCA) which has no surfactant structure, is not structure-forming on its own, the solubility of which in water or oil ranges between 4 g and 1000 g per liter and which does not preferably accumulate at the oil-water interface, c) at least one anionic, cationic, amphoteric and/or non-ionic surfactant, d) at least one polar protic solvent, in particular having hydroxy functionality, e) if necessary one or more auxiliary substance.

    摘要翻译： 一种用于清洁由有机或无机材料制成的物体的方法，其中所述相关材料与流体纳米相系统形式的组合物接触，所述组合物包含：a）至少一种具有小于4的水溶性的水不溶性物质 克/升，b）至少一种不具有表面活性剂结构的两亲物质（NP-MCA）本身不是结构形成的，其在水或油中的溶解度范围为4g至1000g / l，其中 不优选在油 - 水界面处积聚，c）至少一种阴离子，阳离子，两性和/或非离子表面活性剂，d）至少一种极性质子溶剂，特别是具有羟基官能团，e） 更多辅助物质。