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    Non-volatile memory device and methods of manufacturing and operating the same
    1.
    发明申请
    Non-volatile memory device and methods of manufacturing and operating the same 有权
    非易失性存储器件及其制造和操作方法

    公开(公告)号：US20080093649A1

    公开(公告)日：2008-04-24

    申请号：US11698067

    申请日：2007-01-26

    Applicant: Jin-Woo Kim ,  Jong-Hyon Ahn ,  Don-Woo Lee

    Inventor： Jin-Woo Kim ,  Jong-Hyon Ahn ,  Don-Woo Lee

    IPC: H01L29/788

    CPC classification number: H01L29/42336 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11553 ,  H01L29/7885

    Abstract: A non-volatile memory device and methods of manufacturing and operating the same are provided. In a method of manufacturing a non-volatile memory device, a substrate having a stepped portion that may include a first horizontal face, a second horizontal face lower than the first horizontal face, and a vertical face connected between the first and second horizontal faces may be prepared. A first impurity region may be formed under the first horizontal face. A tunnel insulation layer may be continuously formed on the vertical face and the second horizontal face. A floating gate electrode having a tip higher than the first horizontal face may be formed on the tunnel insulation layer. A dielectric layer may be formed on the floating gate electrode. The floating gate electrode may be covered with a control gate electrode. A second impurity region horizontally spaced apart from the floating gate electrode may be formed under the second horizontal face.

    Abstract translation: 提供了一种非易失性存储器件及其制造和操作方法。 在制造非易失性存储器件的方法中，具有阶梯部分的衬底可以包括第一水平面，比第一水平面低的第二水平面和连接在第一和第二水平面之间的垂直面， 准备好 可以在第一水平面下方形成第一杂质区。 隧道绝缘层可以在垂直面和第二水平面上连续地形成。 具有尖端高于第一水平面的浮栅电极可以形成在隧道绝缘层上。 可以在浮栅电极上形成电介质层。 浮栅电极可以用控制栅电极覆盖。 可以在第二水平面下方形成与浮栅电极水平间隔开的第二杂质区域。

    Slew rate boost circuit, output buffer having the same, and method thereof
    4.
    发明授权
    Slew rate boost circuit, output buffer having the same, and method thereof 有权
    压摆率升压电路，具有相同的输出缓冲器及其方法

    公开(公告)号：US08648637B2

    公开(公告)日：2014-02-11

    申请号：US13151891

    申请日：2011-06-02

    Applicant: Min-sung Kim ,  Il-kwon Chang ,  Ji-ho Lew ,  Young-chul Kim ,  Joon-yul Yun ,  Don-woo Lee ,  So-youn Kim ,  Kyung-won Min ,  Jae-hoon Lee

    Inventor： Min-sung Kim ,  Il-kwon Chang ,  Ji-ho Lew ,  Young-chul Kim ,  Joon-yul Yun ,  Don-woo Lee ,  So-youn Kim ,  Kyung-won Min ,  Jae-hoon Lee

    IPC: H03K5/12

    CPC classification number: G09G3/3685 ,  G09G2310/0259 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/0294

    Abstract: A slew rate boost circuit for an output buffer and an output buffer circuit for a source driver having the same are provided. In an output buffer including a pull-up unit providing a buffer output signal in a first level by receiving a buffer input signal and performing pull-up operation and a pull-down unit providing a buffer output signal in a second level having opposite phase from the first level by receiving the buffer input signal and performing pull-down operation, the slew rate boost circuit includes a first comparator generating a first boost signal to boost pull-up operation of the pull-up unit of the output buffer by inputting a first input signal and a second input signal and a second comparator generating a second boost signal to boost pull-down operation of the pull-down unit of the output buffer by inputting the first input signal and the second input signal.

    Abstract translation: 提供了一种用于输出缓冲器的转换速率升压电路和用于其驱动器的输出缓冲电路。 在包括上拉单元的输出缓冲器中，所述上拉单元通过接收缓冲器输入信号并执行上拉操作来提供第一电平的缓冲器输出信号，以及下拉单元，其提供具有相反相位相反相位相反相位的第二电平的缓冲器输出信号 所述第一电平通过接收所述缓冲器输入信号并执行下拉操作，所述转换速率升压电路包括：第一比较器，产生第一升压信号，以通过输入第一升压信号来输出所述输出缓冲器的上拉单元的上拉操作; 输入信号和第二输入信号，第二比较器生成第二升压信号，以通过输入第一输入信号和第二输入信号来提升输出缓冲器的下拉单元的下拉操作。

    Method of fabricating a flash memory cell
    6.
    发明授权
    Method of fabricating a flash memory cell 有权
    制造闪存单元的方法

    公开(公告)号：US07205194B2

    公开(公告)日：2007-04-17

    申请号：US10874579

    申请日：2004-06-24

    Applicant: Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

    Inventor： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

    IPC: H01L21/336

    CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

    Abstract: A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.

    Abstract translation: 一种制造具有分裂栅极结构的闪存单元的方法。 牺牲层形成在形成在半导体衬底上的浮栅上。 牺牲层被蚀刻以形成暴露浮动栅极层的一部分的开口。 在开口内部形成栅极层间绝缘层图案。 在去除牺牲层图案并蚀刻浮栅（使用栅极层间绝缘层图案作为蚀刻掩模）之后，在栅极层间绝缘层图案下方形成浮栅。 控制栅极形成为与浮置栅极的一部分重叠。

    Semiconductor device with split gate electrode structure and method for manufacturing the semiconductor device
    7.
    发明申请
    Semiconductor device with split gate electrode structure and method for manufacturing the semiconductor device 失效
    具有分裂栅电极结构的半导体器件和用于制造半导体器件的方法

    公开(公告)号：US20060027858A1

    公开(公告)日：2006-02-09

    申请号：US11246590

    申请日：2005-10-11

    Applicant: Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

    Inventor： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

    IPC: H01L29/788

    CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11539

    Abstract: A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.

    Abstract translation: 半导体器件包括分为存储单元区域和逻辑区域的衬底。 在基板的存储单元区域中形成分割栅电极结构。 在分离栅电极结构的侧壁和基板的表面上形成氧化硅层。 在位于分离栅电极结构的侧壁上的氧化硅层上形成字线。 字线具有上宽度和下宽度。 较低的宽度大于上部宽度。 在基板的逻辑区域上形成逻辑门图案。 逻辑门图案具有比字线的较低宽度更薄的厚度。

    SLEW RATE BOOST CIRCUIT, OUTPUT BUFFER HAVING THE SAME, AND METHOD THEREOF
    9.
    发明申请
    SLEW RATE BOOST CIRCUIT, OUTPUT BUFFER HAVING THE SAME, AND METHOD THEREOF 有权
    松紧速率升压电路，具有相同功能的输出缓冲器及其方法

    公开(公告)号：US20120013378A1

    公开(公告)日：2012-01-19

    申请号：US13151891

    申请日：2011-06-02

    Applicant: Min-sung KIM ,  II-kwon CHANG ,  Ji-ho LEW ,  Young-chul KIM ,  Joon-yul YUN ,  Don-woo LEE ,  So-youn Kim ,  Kyung-won MIN ,  Jae-hoon LEE

    Inventor： Min-sung KIM ,  II-kwon CHANG ,  Ji-ho LEW ,  Young-chul KIM ,  Joon-yul YUN ,  Don-woo LEE ,  So-youn Kim ,  Kyung-won MIN ,  Jae-hoon LEE

    IPC: H03K5/12

    CPC classification number: G09G3/3685 ,  G09G2310/0259 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/0294

    Abstract: A slew rate boost circuit for an output buffer and an output buffer circuit for a source driver having the same are provided. In an output buffer including a pull-up unit providing a buffer output signal in a first level by receiving a buffer input signal and performing pull-up operation and a pull-down unit providing a buffer output signal in a second level having opposite phase from the first level by receiving the buffer input signal and performing pull-down operation, the slew rate boost circuit includes a first comparator generating a first boost signal to boost pull-up operation of the pull-up unit of the output buffer by inputting a first input signal and a second input signal and a second comparator generating a second boost signal to boost pull-down operation of the pull-down unit of the output buffer by inputting the first input signal and the second input signal.

    Abstract translation: 提供了一种用于输出缓冲器的转换速率升压电路和用于其驱动器的输出缓冲电路。 在包括上拉单元的输出缓冲器中，所述上拉单元通过接收缓冲器输入信号并执行上拉操作来提供第一电平的缓冲器输出信号，以及下拉单元，其提供具有相反相位相反相位相反相位的第二电平的缓冲器输出信号 所述第一电平通过接收所述缓冲器输入信号并执行下拉操作，所述转换速率升压电路包括：第一比较器，产生第一升压信号，以通过输入第一升压信号来输出所述输出缓冲器的上拉单元的上拉操作; 输入信号和第二输入信号，第二比较器生成第二升压信号，以通过输入第一输入信号和第二输入信号来提升输出缓冲器的下拉单元的下拉操作。

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