Method for forming a cleaved facet of semiconductor device
    1.
    发明授权
    Method for forming a cleaved facet of semiconductor device 有权
    用于形成半导体器件的切割面的方法

    公开(公告)号:US08871612B2

    公开(公告)日:2014-10-28

    申请号:US13440640

    申请日:2012-04-05

    IPC分类号: H01L21/301

    摘要: Embodiments disclose a method including forming at least one compound semiconductor layer on a top r-face of a substrate, forming a line for cleavage on a bottom r-face of the substrate along a length of a guide line, wherein the guide line extends in a (11-22)-plane direction of the substrate, wherein the guide line extends from one portion of an edge to another portion of the edge, and wherein the edge is disposed between the top r-face and the bottom r-face of the substrate, and applying a force to the bottom r-face of the substrate to cleave the substrate along the line for cleavage in the (11-22)-plane direction and to form a cleaved facet along a c-plane of the at least one compound semiconductor.

    摘要翻译: 实施例公开了一种方法,包括在基板的顶部r面上形成至少一个化合物半导体层,沿着导向线的长度在基板的底部r面上形成用于切割的线,其中引导线延伸在 基板的(11-22)平面方向,其中所述引导线从边缘的一部分延伸到所述边缘的另一部分,并且其中所述边缘设置在所述边缘的顶部r面和底部r面之间 衬底,并且向衬底的底部r面施加一个力以沿着线切割衬底以在(11-22)平面方向上进行切割,并沿着至少在该平面方向的c面上形成一个切割面 一种化合物半导体。

    METHOD FOR FORMING A CLEAVED FACET OF SEMICONDUCTOR DEVICE
    2.
    发明申请
    METHOD FOR FORMING A CLEAVED FACET OF SEMICONDUCTOR DEVICE 有权
    用于形成半导体器件的清洁表面的方法

    公开(公告)号:US20130217209A1

    公开(公告)日:2013-08-22

    申请号:US13440640

    申请日:2012-04-05

    IPC分类号: H01L21/78

    摘要: Embodiments disclose a method including forming at least one compound semiconductor layer on a top r-face of a substrate, forming a line for cleavage on a bottom r-face of the substrate along a length of a guide line, wherein the guide line extends in a (11-22)-plane direction of the substrate, wherein the guide line extends from one portion of an edge to another portion of the edge, and wherein the edge is disposed between the top r-face and the bottom r-face of the substrate, and applying a force to the bottom r-face of the substrate to cleave the substrate along the line for cleavage in the (11-22)-plane direction and to form a cleaved facet along a c-plane of the at least one compound semiconductor.

    摘要翻译: 实施例公开了一种方法,包括在基板的顶部r面上形成至少一个化合物半导体层,沿着导向线的长度在基板的底部r面上形成用于切割的线,其中引导线延伸在 基板的(11-22)平面方向,其中所述引导线从边缘的一部分延伸到所述边缘的另一部分,并且其中所述边缘设置在所述边缘的顶部r面和底部r面之间 衬底,并且向衬底的底部r面施加一个力以沿着线切割衬底以在(11-22)平面方向上进行切割,并沿着至少在该平面方向的c面上形成一个切割面 一种化合物半导体。

    METHOD FOR FORMING A CLEAVED FACET OF SEMICONDUCTOR DEVICE
    3.
    发明申请
    METHOD FOR FORMING A CLEAVED FACET OF SEMICONDUCTOR DEVICE 有权
    用于形成半导体器件的清洁表面的方法

    公开(公告)号:US20130217162A1

    公开(公告)日:2013-08-22

    申请号:US13440321

    申请日:2012-04-05

    IPC分类号: H01L21/78

    摘要: Embodiments disclose a method including forming at least one compound semiconductor layer on a top r-face of a substrate, forming a line for cleavage on a bottom r-face of the substrate along a length of a guide line, wherein the guide line extends in a (11-20)-plane direction of the substrate, wherein the guide line extends from one portion of an edge to another portion of the edge, and wherein the edge is disposed between the top r-face and the bottom r-face of the substrate, and applying a force to the bottom r-face of the substrate to cleave the substrate along the line for cleavage in the (11-20)-plane direction and to form a cleaved facet along a m-plane of the at least one compound semiconductor.

    摘要翻译: 实施例公开了一种方法,包括在基板的顶部r面上形成至少一个化合物半导体层,沿着导向线的长度在基板的底部r面上形成用于切割的线,其中引导线延伸在 基板的(11-20)平面方向,其中所述引导线从边缘的一部分延伸到所述边缘的另一部分,并且其中所述边缘设置在所述边缘的顶部r面和底部r面之间 并且向衬底的底部r面施加一个力,沿着(11-20)平面方向上的切割线切割衬底,并沿着至少在(11-20))平面方向上的m平面形成切割面 一种化合物半导体。

    Method for forming a cleaved facet of semiconductor device
    5.
    发明授权
    Method for forming a cleaved facet of semiconductor device 有权
    用于形成半导体器件的切割面的方法

    公开(公告)号:US08912528B2

    公开(公告)日:2014-12-16

    申请号:US13440321

    申请日:2012-04-05

    IPC分类号: H01L21/02

    摘要: Embodiments disclose a method including forming at least one compound semiconductor layer on a top r-face of a substrate, forming a line for cleavage on a bottom r-face of the substrate along a length of a guide line, wherein the guide line extends in a (11-20)-plane direction of the substrate, wherein the guide line extends from one portion of an edge to another portion of the edge, and wherein the edge is disposed between the top r-face and the bottom r-face of the substrate, and applying a force to the bottom r-face of the substrate to cleave the substrate along the line for cleavage in the (11-20)-plane direction and to form a cleaved facet along a m-plane of the at least one compound semiconductor.

    摘要翻译: 实施例公开了一种方法,包括在基板的顶部r面上形成至少一个化合物半导体层,沿着导向线的长度在基板的底部r面上形成用于切割的线,其中引导线延伸在 基板的(11-20)平面方向,其中所述引导线从边缘的一部分延伸到所述边缘的另一部分,并且其中所述边缘设置在所述边缘的顶部r面和底部r面之间 并且向衬底的底部r面施加一个力,沿着(11-20)平面方向上的切割线切割衬底,并沿着至少在(11-20))平面方向上的m平面形成切割面 一种化合物半导体。

    LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME
    6.
    发明申请
    LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
    发光装置及其制造方法

    公开(公告)号:US20120241770A1

    公开(公告)日:2012-09-27

    申请号:US13429623

    申请日:2012-03-26

    IPC分类号: H01L33/00

    摘要: Disclosed are a light emitting device, a method for manufacturing the same, a light emitting device package, and a lighting system. The light emitting device includes a first conductive semiconductor layer, an active layer comprising a well layer and a barrier layer on the first conductive layer, and a second conductive semiconductor layer on the active layer. The well layer includes a first well layer closest to the first conductive semiconductor layer and having a first energy bandgap, a third well layer closest to the second conductive semiconductor layer and having a third energy bandgap, and a second well layer interposed between the first and third well layers and having a second energy bandgap. The third energy bandgap of the third well layer is greater than the second energy bandgap of the second well layer.

    摘要翻译: 公开了一种发光器件,其制造方法,发光器件封装和照明系统。 发光器件包括第一导电半导体层,在第一导电层上包括阱层和阻挡层的有源层以及有源层上的第二导电半导体层。 阱层包括最靠近第一导电半导体层并且具有第一能带隙的第一阱层,最靠近第二导电半导体层的第三阱层并具有第三能带隙,以及插入在第一和第二阱层之间的第二阱层, 第三阱层并具有第二能带隙。 第三阱层的第三能带隙大于第二阱层的第二能带隙。