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    Method for analyzing security grade of information property
    3.
    发明授权
    Method for analyzing security grade of information property 失效
    分析信息资产安全等级的方法

    公开(公告)号：US07832013B2

    公开(公告)日：2010-11-09

    申请号：US11081501

    申请日：2005-03-17

    申请人： Won Joo Park ,  Youn Seo Jeong ,  Dong Il Seo

    发明人： Won Joo Park ,  Youn Seo Jeong ,  Dong Il Seo

    IPC分类号： G06F11/00

    CPC分类号： G06F21/577 ,  G06Q10/10

    摘要： A method for analyzing a security grade of an information property, and more particularly, a method by which a security grade (a risk degree in security) is analyzed objectively and quantitatively such that risk degree management of an information property can be efficiently performed, is provided. The method for analyzing a security grade of an information property includes: selecting an information property as an object of security grade analysis, among information properties for which risk degree analysis and importance evaluation in managerial, physical, and technological aspects are performed; calculating the property risk degree of the selected property based on the weighted mean of risk degrees and importance evaluation; and mapping the weighted mean of the risk degree and the importance on a 2-dimensional plane having the X-axis indicating the weighted mean of a risk degree and the Y-axis indicating importance, and based on the appearing result, determining the priority of a safeguard.

    摘要翻译： 更具体地说，一种用于分析信息属性的安全等级的方法，更具体地说，可以客观地和定量地分析安全级别（安全性的风险程度），从而可以有效地执行信息属性的风险度管理的方法是 提供。 用于分析信息属性的安全等级的方法包括：在执行风险度分析和管理，物理和技术方面的重要性评估的信息属性中，选择作为安全等级分析对象的信息属性; 根据风险度和重要度评估的加权平均值计算所选财产的财产风险程度; 并绘制风险度的加权平均值以及具有X轴的二维平面的重要性，该X轴表示风险度的加权平均值，Y轴表示重要性，并且基于出现结果，确定优先级 一个保障。

    Input buffer with wide input voltage range
    4.
    发明申请
    Input buffer with wide input voltage range 审中-公开
    输入缓冲器，输入电压范围宽

    公开(公告)号：US20080211542A1

    公开(公告)日：2008-09-04

    申请号：US12076312

    申请日：2008-03-17

    申请人： Dong-il Seo ,  Hyung-dong Kim ,  Jung-sik Kim

    发明人： Dong-il Seo ,  Hyung-dong Kim ,  Jung-sik Kim

    IPC分类号： H03K19/0185

    CPC分类号： H03K19/018528

    摘要： The input buffer is driven by a data input/output supply voltage. The input buffer generates an output signal from an input signal that swings between the data input/output supply voltage and a data input/output ground voltage.

    摘要翻译： 输入缓冲器由数据输入/输出电源电压驱动。 输入缓冲器从数据输入/输出电源电压和数据输入/输出接地电压之间摆动的输入信号产生输出信号。

    Column select line enable circuit for a semiconductor memory device
    7.
    发明授权
    Column select line enable circuit for a semiconductor memory device 失效
    用于半导体存储器件的列选择线使能电路

    公开(公告)号：US5959936A

    公开(公告)日：1999-09-28

    申请号：US977187

    申请日：1997-11-24

    申请人： Dong-il Seo ,  Tae-seong Jang

    发明人： Dong-il Seo ,  Tae-seong Jang

    IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/413 ,  G11C8/00

    CPC分类号： G11C7/22 ,  G11C7/1072

    摘要： A column select line enable circuit prevents the first bit in a sequence of output data from being missed, thereby reducing tRCD in a synchronous memory device. The circuit delays a predetermined period of time after a row active command is applied to the memory device and then activates a column select enable line regardless of the state of the system clock signal. The column select enable line is maintained in an active state for a second period of time to allow the first bit of data to be read from the device. Thereafter, the column select enable line is enabled and disabled responsive to the system clock signal to read the remaining bits in the sequence of output data in a conventional manner. In a preferred embodiment, the circuit does not enable the column select enable line unless a decoded bank address signal is active.

    摘要翻译： 列选择线使能电路防止输出数据序列中的第一位被错过，从而减少同步存储器件中的tRCD。 在将行活动命令施加到存储器件之后，电路延迟预定的时间段，然后激活列选择使能线，而不管系统时钟信号的状态如何。 列选择使能线在第二时间段内保持在活动状态，以允许从设备读取第一位数据。 此后，响应于系统时钟信号，列选择使能线被使能和禁止，以常规方式读出输出数据序列中的剩余位。 在优选实施例中，除非解码的存储体地址信号有效，否则该电路不启用列选择使能线。

    Boost voltage generator for controlling a memory cell array
    8.
    发明授权
    Boost voltage generator for controlling a memory cell array 失效
    升压电压发生器，用于控制存储单元阵列

    公开(公告)号：US5886933A

    公开(公告)日：1999-03-23

    申请号：US879757

    申请日：1997-06-19

    申请人： Dong-il Seo ,  Hyung-dong Kim

    发明人： Dong-il Seo ,  Hyung-dong Kim

    IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C8/08 ,  G11C11/407 ,  G11C7/00

    CPC分类号： G11C5/143 ,  G11C8/08

    摘要： A boost voltage generating circuit for a memory device prevents excessive voltage on a word line for a memory cell array and reduces power consumption by utilizing an internal array reference voltage signal as a reference signal for the boost voltage generating circuit. The circuit maintains the boost voltage power supply signal at a predetermined level independently of the voltage level of an internal peripheral reference voltage signal which is applied to a peripheral circuit and which can be increased to increase the speed of the memory device without causing excessive voltage on the word line. The boost voltage generating circuit includes a level detector circuit which receives the array reference voltage signal as a reference signal. The boost voltage generating circuit also includes a pulse generator and a pumping circuit which utilize the array reference voltage signal as a power supply.

    摘要翻译： 用于存储器件的升压电压产生电路防止用于存储单元阵列的字线上的过高电压，并且通过利用内部阵列参考电压信号作为升压电压产生电路的参考信号来降低功耗。 该电路将升压电压电源信号保持在预定电平，独立于施加到外围电路的内部周边参考电压信号的电压电平，并且可以增加以提高存储器件的速度，而不会导致过高的电压 字线。 升压电压产生电路包括电平检测器电路，其接收阵列参考电压信号作为参考信号。 升压电压产生电路还包括利用阵列参考电压信号作为电源的脉冲发生器和泵浦电路。

    Semiconductor memory device with variable plate voltage generator
    9.
    发明授权
    Semiconductor memory device with variable plate voltage generator 失效
    具有可变板电压发生器的半导体存储器件

    公开(公告)号：US5777934A

    公开(公告)日：1998-07-07

    申请号：US674705

    申请日：1996-07-08

    申请人： Sang-bo Lee ,  Dong-il Seo

    发明人： Sang-bo Lee ,  Dong-il Seo

    IPC分类号： G11C11/417 ,  G11C5/14 ,  G11C11/404 ,  G11C11/407 ,  G11C11/4074 ,  G11C8/00

    CPC分类号： G11C11/4074

    摘要： A semiconductor memory device achieves high speed operation while operating at a low power supply voltage by boosting the voltage level at the plate node of a memory cell during an access operation. The memory device includes a plate voltage generator which generates a variable voltage level. The plate voltage generator includes a pair of switches for coupling the plate node to either a conventional (1/2)VCC voltage generator or a power supply node in response to a control signal. The plate voltage generator also includes a pulse generator that generates a pulse signal for controlling the switches in response to the control signal. During a precharge period, the bitline pair is charged to VCC. The plate voltage generator charges the plate node to (1/2)VCC during the precharge state and then to VCC during an access operation. This boosts the voltage level at the storage node of the memory cell, thereby decreasing the time required to amplify the signals on the bitlines.

    摘要翻译： 半导体存储器件在访问操作期间通过升高存储器单元的板节点处的电压电平，在低电源电压下工作，实现高速操作。 存储器件包括产生可变电压电平的板电压发生器。 板电压发生器包括一对开关，用于响应于控制信号将板节点耦合到常规（+ E，fra 1/2 + EE）VCC电压发生器或电源节点。 板电压发生器还包括脉冲发生器，其产生用于响应于控制信号控制开关的脉冲信号。 在预充电期间，位线对被充电到VCC。 板电压发生器在预充电状态期间将板节点充电到（+ E，fra 1/2 + EE）VCC，然后在访问操作期间向VCC充电。 这提高了存储单元的存储节点处的电压电平，从而减少放大位线上的信号所需的时间。

    Solenoid valve for brake system
    10.
    发明授权
    Solenoid valve for brake system 有权
    制动系统电磁阀

    公开(公告)号：US08375985B2

    公开(公告)日：2013-02-19

    申请号：US12051978

    申请日：2008-03-20

    申请人： Chung Jae Lee ,  Dong Il Seo ,  Sang Cheol Lee

    发明人： Chung Jae Lee ,  Dong Il Seo ,  Sang Cheol Lee

    IPC分类号： F16K31/06

    CPC分类号： F16K31/0658 ,  B60T8/363 ,  Y10T137/8122

    摘要： A solenoid valve for a brake system capable of being easily manufactured with reduced manufacturing costs is disclosed. A valve seat member has an inner passage formed through the valve seat member in a longitudinal direction thereof, an outer passage formed on an outer surface of the valve seat member in the longitudinal direction, and a seat portion formed with a first orifice above the inner passage. The seat portion is formed unitarily with the valve seat member. A sleeve is coupled on the outer surface of the valve seat member. The sleeve has a flange portion to be fixed to a modulator block. A valve core is coupled to a portion of the sleeve, opposite to the flange portion. An armature is slidably mounted in the sleeve. The armature has an opening/closing portion to open or close the first orifice. A restoring spring presses the armature toward the first orifice.

    摘要翻译： 公开了一种用于制造系统的电磁阀，其能够以降低的制造成本容易地制造。 阀座构件具有沿着阀座构件的长度方向形成的内部通路，形成在阀座构件的长度方向的外表面上的外部通路，以及在内部形成有第一孔的座部 通道。 座部与阀座构件一体地形成。 套筒联接在阀座构件的外表面上。 套筒具有固定到调制器块的凸缘部分。 阀芯联接到与凸缘部分相对的套筒的一部分。 电枢可滑动地安装在套筒中。 衔铁具有用于打开或关闭第一孔口的打开/关闭部分。 复位弹簧将电枢朝向第一孔压。