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1.发明授权公开(公告)号：US06831924B1
公开(公告)日：2004-12-14
申请号：US09620333
申请日：2000-07-20
申请人： Frank N. Cornett , Philip N. Jenkins , Terrance L. Bowman , Joseph M. Placek , Gregory M. Thorson
发明人： Frank N. Cornett , Philip N. Jenkins , Terrance L. Bowman , Joseph M. Placek , Gregory M. Thorson
IPC分类号： H04L1256
CPC分类号： H04L5/1415 , H04L5/14 , H04L5/16
摘要： A variable communication systems comprising a plurality of transceivers and a control circuit connected to the transceivers to configure the transceivers to operate in a bi-directional mode and a uni-directional mode at different times using different transfer methods to transfer data.
摘要翻译： 一种可变通信系统，包括多个收发器和连接到收发器的控制电路，以配置收发器在不同的时间使用不同的传输方法传输数据的双向模式和单向模式。
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2.发明授权Method and apparatus for communicating computer data from one point to another over a communications medium 有权用于通过通信介质将计算机数据从一个点传送到另一个点的方法和装置公开(公告)号：US07248635B1
公开(公告)日：2007-07-24
申请号：US09620373
申请日：2000-07-20
申请人： Michael R. Arneson , Terrance L. Bowman , Frank N. Cornett , John F. DeRyckere , Brian T. Hillert , Philip N. Jenkins , Nan Ma , Joseph M. Placek , Rodney Ruesch , Gregory M. Thorson
发明人： Michael R. Arneson , Terrance L. Bowman , Frank N. Cornett , John F. DeRyckere , Brian T. Hillert , Philip N. Jenkins , Nan Ma , Joseph M. Placek , Rodney Ruesch , Gregory M. Thorson
CPC分类号： H04L25/03878 , H04L25/0278 , H04L25/028 , H04L25/0292
摘要： The present invention is directed toward a communications channel comprising a link level protocol, a driver, a receiver, and a canceller/equalizer. The link level protocol provides logic for DC-free signal encoding and recovery as well as supporting many features including CRC error detection and message resend to accommodate infrequent bit errors across the medium. The canceller/equalizer provides equalization for destabilized data signals and also provides simultaneous bi-directional data transfer. The receiver provides bit deskewing by removing synchronization error, or skewing, between data signals. The driver provides impedance controlling by monitoring the characteristics of the communications medium, like voltage or temperature, and providing a matching output impedance in the signal driver so that fewer distortions occur while the data travels across the communications medium.
摘要翻译： 本发明涉及包括链路级协议，驱动器，接收机和消除器/均衡器的通信信道。 链路级协议提供了无DC信号编码和恢复的逻辑，并支持许多功能，包括CRC错误检测和消息重发，以适应介质上不常见的位错误。 消除器/均衡器为不稳定的数据信号提供均衡，并且还提供同时的双向数据传输。 接收器通过消除数据信号之间的同步错误或倾斜来提供位去偏移。 驱动器通过监视通信介质的特性（如电压或温度）以及在信号驱动器中提供匹配的输出阻抗来提供阻抗控制，以便在数据传播通过通信介质时发生较少的失真。
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3.发明授权System and method of synchronizing real time clock values in arbitrary distributed systems 有权在任意分布式系统中同步实时时钟值的系统和方法公开(公告)号：US08498315B2
公开(公告)日：2013-07-30
申请号：US13270002
申请日：2011-10-10
IPC分类号： H04J3/06
摘要： A system for establishing a primary master node in a computer system includes a plurality of nodes, each node configured with an update interval, a hierarchy of master nodes selected from the plurality of nodes, wherein the master nodes are configured to synchronize the plurality of nodes with a clock value by sending out its clock value when its update interval has expired, wherein each node resets its update interval when it receives the clock value, a primary master node selected from the hierarchy of master nodes based on its update interval, and at least one backup master node selected from the hierarchy of master nodes based on its update interval, the backup master node configured to become the primary master node when the plurality of nodes do not receive the clock value after a predetermined period of time has elapsed.
摘要翻译： 用于在计算机系统中建立主主节点的系统包括多个节点，配置有更新间隔的每个节点，从多个节点中选择的主节点的层次结构，其中主节点被配置为同步多个节点 通过在其更新间隔到期时发送其时钟值，其中每个节点在其接收时钟值时重置其更新间隔，基于其更新间隔从主节点的层次结构中选择的主主节点，以及 基于其更新间隔从主节点的层次结构中选择的至少一个备用主节点，所述备用主节点被配置为当所述多个节点在经过预定时间段之后未接收到所述时钟值时成为所述主主节点。
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4.发明申请System and Method of Synchronizing Real Time Clock Values in Arbitrary Distributed Systems 有权在任意分布式系统中同步实时时钟值的系统和方法公开(公告)号：US20120089709A1
公开(公告)日：2012-04-12
申请号：US13270002
申请日：2011-10-10
IPC分类号： G06F15/177
摘要： A system for establishing a primary master node in a computer system includes a plurality of nodes, each node configured with an update interval, a hierarchy of master nodes selected from the plurality of nodes, wherein the master nodes are configured to synchronize the plurality of nodes with a clock value by sending out its clock value when its update interval has expired, wherein each node resets its update interval when it receives the clock value, a primary master node selected from the hierarchy of master nodes based on its update interval, and at least one backup master node selected from the hierarchy of master nodes based on its update interval, the backup master node configured to become the primary master node when the plurality of nodes do not receive the clock value after a predetermined period of time has elapsed.
摘要翻译： 用于在计算机系统中建立主主节点的系统包括多个节点，配置有更新间隔的每个节点，从多个节点中选择的主节点的层次结构，其中主节点被配置为同步多个节点 通过在其更新间隔到期时发送其时钟值，其中每个节点在其接收时钟值时重置其更新间隔，基于其更新间隔从主节点的层次结构中选择的主主节点，以及 基于其更新间隔从主节点的层次结构中选择的至少一个备用主节点，所述备用主节点被配置为当所述多个节点在经过预定时间段之后未接收到所述时钟值时成为所述主主节点。
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5.发明申请System and Method of Synchronizing Real Time Clock Values in Arbitrary Distributed Systems 有权在任意分布式系统中同步实时时钟值的系统和方法公开(公告)号：US20080168182A1
公开(公告)日：2008-07-10
申请号：US11620215
申请日：2007-01-05
摘要： A system and method of determining a master node in a computer system having a plurality of nodes includes establishing a hierarchy of master nodes from the plurality of nodes, wherein the master node synchronizes the plurality of nodes in the computer system with a clock value and determining the master node from the hierarchy of master nodes. A system and method of synchronizing a plurality of nodes in a computer system includes determining a master node from the plurality of nodes, sending a clock value from the master node to neighbor nodes of the master node, synchronizing a node clock in each node receiving the clock value if a predetermined period of time has elapsed in each receiving node, distributing a node clock value from each synchronized node to neighbor nodes of the synchronized node, and repeating synchronizing and distributing, wherein synchronizing a node clock in each node receiving the clock value includes each node receiving the node clock value.
摘要翻译： 一种确定具有多个节点的计算机系统中的主节点的系统和方法包括从所述多个节点建立主节点的层次结构，其中所述主节点将所述计算机系统中的所述多个节点与时钟值同步并确定 主节点从主节点的层次结构。 在计算机系统中同步多个节点的系统和方法包括从多个节点确定主节点，从主节点向主节点的邻居节点发送时钟值，使得接收到节点的每个节点中的节点时钟同步 在每个接收节点中经过预定时间段的时钟值，将来自每个同步节点的节点时钟值分配给同步节点的相邻节点，并且重复同步和分配，其中，同步接收时钟值的每个节点中的节点时钟 包括接收节点时钟值的每个节点。
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6.发明授权System and method of synchronizing real time clock values in arbitrary distributed systems 有权在任意分布式系统中同步实时时钟值的系统和方法公开(公告)号：US08036247B2
公开(公告)日：2011-10-11
申请号：US11620215
申请日：2007-01-05
IPC分类号： H04J3/06
摘要： A system and method of determining a master node in a computer system having a plurality of nodes includes establishing a hierarchy of master nodes from the plurality of nodes, wherein the master node synchronizes the plurality of nodes in the computer system with a clock value and determining the master node from the hierarchy of master nodes. A system and method of synchronizing a plurality of nodes in a computer system includes determining a master node from the plurality of nodes, sending a clock value from the master node to neighbor nodes of the master node, synchronizing a node clock in each node receiving the clock value if a predetermined period of time has elapsed in each receiving node, distributing a node clock value from each synchronized node to neighbor nodes of the synchronized node, and repeating synchronizing and distributing, wherein synchronizing a node clock in each node receiving the clock value includes each node receiving the node clock value.
摘要翻译： 一种确定具有多个节点的计算机系统中的主节点的系统和方法包括从所述多个节点建立主节点的层级，其中所述主节点将所述计算机系统中的所述多个节点与时钟值同步并确定 主节点从主节点的层次结构。 在计算机系统中同步多个节点的系统和方法包括从多个节点确定主节点，从主节点向主节点的邻居节点发送时钟值，使得接收到节点的每个节点中的节点时钟同步 在每个接收节点中经过预定时间段的时钟值，将来自每个同步节点的节点时钟值分配给同步节点的相邻节点，并且重复同步和分配，其中，同步接收时钟值的每个节点中的节点时钟 包括接收节点时钟值的每个节点。
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公开(公告)号：US20090259696A1
公开(公告)日：2009-10-15
申请号：US12330413
申请日：2008-12-08
申请人： John Carter , Randal S. Passint , Donglai Dai , Zhen Fang , Lixin Zhang , Gregory M. Thorson
发明人： John Carter , Randal S. Passint , Donglai Dai , Zhen Fang , Lixin Zhang , Gregory M. Thorson
IPC分类号： G06F17/30
CPC分类号： G06F15/16 , Y10S707/99952
摘要： A method and apparatus for controlling access by a set of accessing nodes to memory of a home node (in a multimode computer system) determines that each node in the set of nodes has accessed the memory, and forwards a completion message to each node in the set of nodes after it is determined that each node has accessed the memory. The completion message has data indicating that each node in the set of nodes has accessed the memory of the home node.
摘要翻译： 用于控制一组访问节点对家庭节点（在多模式计算机系统中）的存储器的访问的方法和装置确定该组节点中的每个节点已经访问了存储器，并将完成消息转发到 在确定每个节点已访问存储器之后，节点集合。 完成消息具有指示节点集合中的每个节点已经访问了家庭节点的存储器的数据。
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8.发明授权Multiprocessor system utilizing multiple links to improve point to point bandwidth 有权多处理器系统利用多个链路来提高点对点带宽公开(公告)号：US06643764B1
公开(公告)日：2003-11-04
申请号：US09620372
申请日：2000-07-20
IPC分类号： G06F15163
CPC分类号： H04L45/302 , H04L45/00 , H04L45/22 , H04L45/742
摘要： A multiprocessor computer system comprises a plurality of processing element nodes and an interconnect network interconnecting the plurality of processing element nodes. An interface circuit is associated with each one of the plurality of processing element nodes. The interface circuit has a lookup table having n-number of routing entries for a given destination node. Each one of the n-number of routing entries associated with a different class of traffic. The network traffic is routed according to the class.
摘要翻译： 多处理器计算机系统包括多个处理单元节点和互连多个处理单元节点的互连网络。 接口电路与多个处理元件节点中的每一个相关联。 接口电路具有用于给定目的地节点的具有n个路由条目的查找表。 与不同类别的流量相关联的n个路由条目中的每一个。 网络流量根据类进行路由。
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公开(公告)号：US06578115B2
公开(公告)日：2003-06-10
申请号：US10047347
申请日：2002-01-14
IPC分类号： G06F1208
CPC分类号： G06F11/2051 , G06F12/0808 , G06F12/0817
摘要： A node controller (12) in a computer system (10) includes a processor interface unit (24), a memory directory interface unit (22), and a local block unit (28). In response to a memory location in a memory (17) associated with the memory directory interface unit (22) being altered, the processor interface unit (24) generates an invalidation request for transfer to the memory directory interface unit (22). The memory directory interface unit (22) provides the invalidation request and identities of processors (16) affected by the invalidation request to the local block unit (28). The local block unit (28) determines which ones of the identified processors (16) are present in the computer system (10) and generates an invalidation message for each present processor (16) for transfer thereto. Each of the present processors (16) process their invalidation message and generate an acknowledgment message for transfer to the processor interface unit (24) that generated the invalidation request. The local block unit (28) determines which ones of the identified processors (16) are not present in the computer system (10) and generates an acknowledgment message for each non-existent processor (16). Each acknowledgment message is transferred to the processor interface unit (24) which generated the invalidation request.
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10.发明授权Method and apparatus for handling invalidation requests to processors not present in a computer system 有权用于处理对计算机系统中不存在的处理器的无效请求的方法和装置公开(公告)号：US06339812B1
公开(公告)日：2002-01-15
申请号：US09410139
申请日：1999-09-30
IPC分类号： G06F1208
CPC分类号： G06F11/2051 , G06F12/0808 , G06F12/0817
摘要： A node controller (12) in a computer system (10) includes a processor interface unit (24), a memory directory interface unit (22), and a local block unit (28). In response to a memory location in a memory (17) associated with the memory directory interface unit (22) being altered, the processor interface unit (24) generates an invalidation request for transfer to the memory directory interface unit (22). The memory directory interface unit (22) provides the invalidation request and identities of processors (16) affected by the invalidation request to the local block unit (28). The local block unit (28) determines which ones of the identified processors (16) are present in the computer system (10) and generates an invalidation message for each present processor (16) for transfer thereto. Each of the present processors (16) process their invalidation message and generate an acknowledgment message for transfer to the processor interface unit (24) that generated the invalidation request. The local block unit (28) determines which ones of the identified processors (16) are not present in the computer system (10) and generates an acknowledgment message for each non-existent processor (16). Each acknowledgment message is transferred to the processor interface unit (24) which generated the invalidation request.
摘要翻译： 计算机系统（10）中的节点控制器（12）包括处理器接口单元（24），存储器目录接口单元（22）和局部块单元（28）。 响应于与存储器目录接口单元（22）相关联的存储器（17）中的存储器位置被改变，处理器接口单元（24）生成用于传送到存储器目录接口单元（22）的无效请求。 存储器目录接口单元（22）将无效请求和无效请求影响的处理器（16）的标识提供给本地块单元（28）。 本地块单元（28）确定在计算机系统（10）中存在哪个已识别的处理器（16），并为每个当前处理器（16）生成用于传送的无效消息。 本处理器（16）中的每一个处理它们的无效消息，并产生用于传送到产生无效请求的处理器接口单元（24）的确认消息。 本地块单元（28）确定在计算机系统（10）中哪个识别的处理器（16）不存在，并为每个不存在的处理器（16）生成确认消息。 每个确认消息被传送到产生无效请求的处理器接口单元（24）。
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