公开(公告)号：US06255913B1

公开(公告)日：2001-07-03

申请号：US09412462

申请日：1999-10-04

申请人： Hongmo Wang

发明人： Hongmo Wang

IPC分类号： H03J524

CPC分类号： H03B5/08 ,  H03B2201/0208 ,  H03B2201/0216 ,  H03B2201/025

摘要： A variable frequency oscillator (VFO) circuit having an increased frequency tuning range to selectively obtain operating frequencies above and below a set frequency. The circuit includes a tank inductor connected in parallel with a tank capacitor for primarily defining the set oscillating frequency of the VFO circuit. A switchable capacitor is included for selectively providing a predetermined step-wise decrease of the oscillating frequency to a frequency value below the set frequency of the circuit, and a varactor is included for accommodating selective tuning of the oscillating frequency within a range of frequency values below the set frequency. The inventive circuit selectively includes a switchable inductance element which is selectively electromagnetically coupled to the tank inductor to decrease the overall inductance value of the VFO circuit and, thereby, selectively increase the oscillating frequency above the set frequency value.

摘要翻译： 一种具有增加的频率调谐范围的可变频率振荡器（VFO）电路，以选择性地获得高于和低于设定频率的工作频率。 该电路包括与电容器并联连接的电容器，用于主要限定VFO电路的设定振荡频率。 包括可切换电容器，用于选择性地将振荡频率的预定逐步降低降低到低于电路设定频率的频率值，并且包括变容二极管，用于适应频率值范围内的振荡频率的选择性调谐 设定频率。 本发明的电路选择性地包括可切换电感元件，其可选择性地电磁耦合到电容器电感器以减小VFO电路的整体电感值，从而选择性地将振荡频率提高到设定频率值以上。

公开(公告)号：US6166571A

公开(公告)日：2000-12-26

申请号：US368299

申请日：1999-08-03

申请人： Hongmo Wang

发明人： Hongmo Wang

IPC分类号： H03K3/356 ,  H03K3/3562 ,  H03K23/44 ,  H03K25/00

CPC分类号： H03K3/35625 ,  H03K3/356139 ,  H03K23/44

摘要： A high frequency divider circuit for producing output signals of half the frequency of an input clock signal includes two identical circuit sections, each producing an output signal and its complement. The circuit sections are connected to each other so that the output signals of one circuit section serve as input signals to the other circuit section. Each circuit section contains a load transistor which is controlled by one of the clock signal and the clock signal complement, and a switch transistor which is controlled by the other of the clock signal and the clock signal complement. The inventive circuit exhibits a reduced RC time constant for each circuit section and an increased output signal swing between the output signals and their respective complements, as contrasted with prior art frequency dividers, thereby increasing the overall circuit response time and its ability to operate at high frequencies.

摘要翻译： 用于产生输入时钟信号的一半频率的输出信号的高分频器电路包括两个相同的电路部分，每个产生输出信号及其补码。 电路部分彼此连接，使得一个电路部分的输出信号用作到另一个电路部分的输入信号。 每个电路部分包含由时钟信号和时钟信号补码中的一个控制的负载晶体管，以及由另一个时钟信号和时钟信号补码控制的开关晶体管。 与现有技术的分频器相比，本发明的电路对于每个电路部分表现出减小的RC时间常数和输出信号与它们各自的补码之间的增加的输出信号摆幅，由此增加总体电路响应时间及其在高电平下的操作能力 频率

公开(公告)号：US6049248A

公开(公告)日：2000-04-11

申请号：US220980

申请日：1998-12-23

申请人： Jack Glas ,  Hongmo Wang

发明人： Jack Glas ,  Hongmo Wang

IPC分类号： H03F1/02 ,  H03F3/217 ,  H03F3/38

CPC分类号： H03F1/0211 ,  H03F3/2171

摘要： A circuit for receiving an input signal having a phase component and an amplitude component which carry information, and for producing an output driver signal containing the phase and amplitude component information for driving a non-linear amplifier for generating linear amplification. The circuit includes a voltage controlled oscillator for receiving the phase component and for outputting a phase modulated carrier signal having a duty cycle and a constant amplitude. A driver stage made from a plurality of invertors, each having a pair of MOSFET transistors, receives the carrier signal at the gate terminals of the transistors. The amplitude component is used to drive the invertors by applying the amplitude component to the backgate terminals of at least some of the transistors in the invertors to pulse width modulate the carrier signal. The resulting output signal containing both phase component information and amplitude component information can then be used to drive a non-linear Class S amplifier to generate linear amplification while achieving high efficiency.

摘要翻译： 一种用于接收具有携带信息的相位分量和振幅分量的输入信号的电路，并且用于产生包含驱动用于产生线性放大的非线性放大器的相位和幅度分量信息的输出驱动器信号。 该电路包括用于接收相位分量并用于输出具有占空比和恒定幅度的相位调制载波信号的压控振荡器。 由具有一对MOSFET晶体管的多个反相器制成的驱动器级在晶体管的栅极端子处接收载波信号。 振幅分量用于通过将反相器中的至少一些晶体管的背栅极端子施加振幅分量来驱动逆变器，以对载波信号进行脉冲宽度调制。 包含相位分量信息和幅度分量信息的所得输出信号随后可用于驱动非线性S类放大器以产生线性放大，同时实现高效率。

公开(公告)号：US6130564A

公开(公告)日：2000-10-10

申请号：US294695

申请日：1999-04-19

申请人： Hongmo Wang

发明人： Hongmo Wang

IPC分类号： H03K23/44 ,  H03K23/54 ,  H03B19/00

CPC分类号： H03K23/44 ,  H03K23/54

摘要： A frequency divider circuit operable at high frequencies for producing an output signal having a frequency value equal to substantially half the frequency value of a clock signal from which the circuit operates. The circuit includes a first transistor branch, an inventor and a second transistor branch. The first transistor branch is connected to an input of the inventor and the second transistor branch is connected to an output of the inventor. The first transistor branch receives a plurality of input signals including the clock signal, a compliment of the clock signal, and the circuit output signal and produces an input signal which is provided to the inventor. The second transistor branch receives a plurality of inputs including the compliment of the clock signal, the clock signal and the inventor output signal, and produces the circuit output signal. The circuit is configured such that the next inventor state is always available for conveyance to the output signal upon a change in the clock signal.

摘要翻译： 一种分频器电路，可在高频下工作，用于产生具有等于电路工作的时钟信号频率的基本上一半的频率值的输出信号。 该电路包括第一晶体管支路，发明者和第二晶体管支路。 第一晶体管支路连接到本发明的输入端，第二晶体管支路连接到本发明的输出端。 第一晶体管分支接收包括时钟信号，时钟信号的补充和电路输出信号的多个输入信号，并产生提供给发明人的输入信号。 第二晶体管分支接收包括时钟信号，时钟信号和发明者输出信号的补充的多个输入，并产生电路输出信号。 电路被配置为使得下一个发明者状态总是可用于在时钟信号的改变时传送到输出信号。

公开(公告)号：US6064264A

公开(公告)日：2000-05-16

申请号：US159294

申请日：1998-09-23

申请人： Maurice J. Tarsia ,  Hongmo Wang

发明人： Maurice J. Tarsia ,  Hongmo Wang

IPC分类号： H03F1/02 ,  H03F3/72 ,  H03F3/16 ,  H03F3/68

CPC分类号： H03F1/0277 ,  H03F3/72

摘要： A switched power amplifier circuit employs non-linear amplifier stages including MOSFET transistors. The transistors each have source, gate, drain and backgate terminals. An input Rf signal is applied to the gate terminals and the source (or drain) terminals are connected to a load. The transistors are operated as switches by selectively applying clock signals to the backgate terminals to activate desired transistors, thus causing the transistors to turn on and allow current to flow through the load to generate power. The power to the load is increased by turning on multiple transistors at any given time.

摘要翻译： 开关功率放大器电路采用包括MOSFET晶体管的非线性放大器级。 晶体管各有源极，栅极，漏极和背栅极端子。 输入Rf信号施加到栅极端子，源极（或漏极）端子连接到负载。 晶体管通过选择性地将时钟信号施加到背栅极端子来激活期望的晶体管，从而使晶体管导通并允许电流流过负载以产生功率，来作为开关来操作。 在任何给定时间通过接通多个晶体管来增加负载的功率。

公开(公告)号：US5959504A

公开(公告)日：1999-09-28

申请号：US37337

申请日：1998-03-10

申请人： Hongmo Wang

发明人： Hongmo Wang

IPC分类号： H03B5/12 ,  H03K3/354 ,  H03B7/02

CPC分类号： H03K3/354

摘要： A voltage controlled oscillator (VCO) CMOS circuit wherein back gate terminals of CMOS transistors are used to vary the parasitic capacitances of the transistors. The back gate terminals receive a signal from a variable voltage source so that oscillation can be controlled by adjusting the variable voltage. The CMOS transistors are connected across an inductor and the transconductance characteristics of the transistors reduce the resistance of the inductor, thereby improving circuit oscillation and providing enhanced stability and capabilities at high operating frequencies.

摘要翻译： 压控振荡器（VCO）CMOS电路，其中CMOS晶体管的背栅极用于改变晶体管的寄生电容。 背栅极端子接收来自可变电压源的信号，从而可以通过调节可变电压来控制振荡。 CMOS晶体管连接在电感上，晶体管的跨导特性降低了电感的电阻，从而改善了电路振荡，并在高工作频率下提供了增强的稳定性和能力。

公开(公告)号：US06229406B1

公开(公告)日：2001-05-08

申请号：US09409150

申请日：1999-09-30

申请人： Hongmo Wang

发明人： Hongmo Wang

IPC分类号： H03B512

CPC分类号： H03B5/1228 ,  H03B5/1203 ,  H03B5/1212 ,  H03B5/124

摘要： An oscillator circuit for increasing the signal power of a generated oscillating signal while decreasing phase noise. The circuit includes an oscillating stage having an inductor and capacitors for producing a periodic oscillating signal and a first control signal. An active stage having a transistor with a gate terminal, a source terminal and a drain terminal is connected to the oscillating stage so that the first control signal is provided to the source terminal of the transistor. A second control signal is provided to the transistor gate terminal for increasing the voltage applied to the gate terminal when the first control signal decreases the voltage applied to the source terminal, thus controlling the activation of the transistor for supplying signal boosting power to the tank stage.

摘要翻译： 一种用于在降低相位噪声的同时增加产生的振荡信号的信号功率的振荡器电路。 该电路包括具有用于产生周期性振荡信号和第一控制信号的电感器和电容器的振荡级。 具有栅极端子，源极端子和漏极端子的晶体管的有源级连接到振荡级，使得第一控制信号被提供给晶体管的源极端子。 当第一控制信号降低施加到源极端子的电压时，第二控制信号被提供给晶体管栅极端子，用于增加施加到栅极端子的电压，从而控制晶体管的激活，以向槽级提供信号提升功率 。

公开(公告)号：US6064262A

公开(公告)日：2000-05-16

申请号：US160932

申请日：1998-09-25

申请人： Hongmo Wang

发明人： Hongmo Wang

IPC分类号： H03F3/45

CPC分类号： H03F3/45654 ,  H03F2203/45342

摘要： A differential amplifier for amplifying the difference between first and second input signals and producing therefrom a differential output signal. The differential amplifier includes first and second transistors connected to a common DC current source and receiving, at the transistor gate terminals, the respective first and second input signals. Each transistor has a common mode voltage associated therewith. A voltage control circuit generates control signals that are applied to the backgate terminals of the transistors to calibrate the differential output voltage and to adjust the common mode voltages of the transistors.

摘要翻译： 一种差分放大器，用于放大第一和第二输入信号之间的差异并由此产生差分输出信号。 差分放大器包括连接到公共DC电流源的第一和第二晶体管，并且在晶体管栅极端处接收相应的第一和第二输入信号。 每个晶体管具有与其相关联的共模电压。 电压控制电路产生施加到晶体管的背栅极端子的控制信号，以校准差分输出电压并调节晶体管的共模电压。

公开(公告)号：US5767726A

公开(公告)日：1998-06-16

申请号：US734658

申请日：1996-10-21

申请人： Hongmo Wang

发明人： Hongmo Wang

IPC分类号： H03D7/00 ,  H03D7/12 ,  H03D7/14 ,  H04B1/26 ,  G06F7/44

CPC分类号： H03D7/125 ,  H03D7/1441 ,  H03D7/1458 ,  H03D2200/0043 ,  H03D2200/0084

摘要： A four terminal multiplication circuit capable of mixing up to three input signals. The circuit includes a MOS transistor having gate, source, drain and back-gate terminals. When the circuit is used as an RF mixer or downconverter, an RF signal is provided to the gate terminal and a local oscillator signal is provided to the back-gate terminal. A DC voltage is applied to the source terminal for biasing the transistor and the mixed/downconverted output (IF) signal is obtained from the drain terminal. A single balanced and a double balanced mixer circuit are also disclosed. In the single balanced circuit, two MOS transistors are used; the RF signal is applied to the gate terminals with the positive phase LO component applied to one back-gate terminal and the negative phase local oscillator (LO) component applied to the other back-gate terminal for producing a positive phase and a negative phase IF signal. In the double balanced circuit, four MOS transistors are used; the positive phase RF signal is applied to the gate terminals of two of the transistors and the negative phase RF signal is applied to the gate terminals of the other two transistors. Likewise, the positive phase LO signal is applied to two of the transistors and the negative phase LO signal is applied to the other two transistors.

摘要翻译： 能够混合多达三个输入信号的四端倍增电路。 该电路包括具有栅极，源极，漏极和背栅极端子的MOS晶体管。 当电路用作RF混频器或下变频器时，将RF信号提供给栅极端子，并将本地振荡器信号提供给后栅极端子。 直流电压施加到源极端子以偏置晶体管，并且从漏极端子获得混合/下变频输出（IF）信号。 还公开了单个平衡和双平衡混频器电路。 在单个平衡电路中，使用两个MOS晶体管; 将RF信号施加到栅极端子，其中正相LO分量施加到一个背栅极端子，并且施加到另一个背栅极端子的负相位本地振荡器（LO）分量用于产生正相和负相位IF 信号。 在双平衡电路中，使用四个MOS晶体管; 正相RF信号施加到两个晶体管的栅极端子，负相位RF信号施加到另外两个晶体管的栅极端子。 同样，正相LO信号被施加到两个晶体管，负相位LO信号被施加到另外两个晶体管。

公开(公告)号：US5608796A

公开(公告)日：1997-03-04

申请号：US386578

申请日：1995-02-10

申请人： Mihai Banu ,  Hongmo Wang

发明人： Mihai Banu ,  Hongmo Wang

IPC分类号： H03L7/00 ,  H03D3/06 ,  H03H11/22 ,  H04L27/22 ,  H04L27/38 ,  H03F3/04

CPC分类号： H03H11/22

摘要： Disclosed is an integrated circuit comprising a balanced set of inputs and a phase splitting circuit. The phase splitting circuit has a first input terminal that is coupled to the balanced set of inputs and a second input terminal that is coupled to the balanced set of inputs. The phase splitting circuit further comprises a balanced phase shifting network, a first set of output terminals, and a second set of output terminals. The balanced phase shifting network is coupled to the first: input terminal and the second input terminal. The first set of output terminals provides a voltage representative of a first voltage across a resistive portion of the balanced phase shifting network in response to an input voltage at the balanced set of inputs. The second set of output terminals provides a voltage representative of a second voltage across a reactive portion of the balanced phase shifting network in response to the input voltage at the balanced set of inputs.

摘要翻译： 公开了一种集成电路，其包括平衡输入集合和相分离电路。 相位分离电路具有耦合到平衡输入集合的第一输入端子和耦合到平衡输入集合的第二输入端子。 相分离电路还包括平衡相移网络，第一组输出端子和第二组输出端子。 平衡相移网络耦合到第一：输入端子和第二输入端子。 第一组输出端子响应于平衡输入集合处的输入电压而提供代表平衡相移网络的电阻部分上的第一电压的电压。 第二组输出端子响应于平衡输入集合处的输入电压而提供代表平衡相移网络的无功部分的第二电压的电压。