公开(公告)号：US06495432B2

公开(公告)日：2002-12-17

申请号：US09834268

申请日：2001-04-12

Applicant: Chi-Chun Chen ,  Horng-Chih Lin ,  Chun-Yen Chang ,  Tiao-Yuan Huang

Inventor： Chi-Chun Chen ,  Horng-Chih Lin ,  Chun-Yen Chang ,  Tiao-Yuan Huang

IPC: H01L21336

CPC classification number: H01L29/66575 ,  H01L21/26513 ,  H01L21/823842

Abstract: A method of reducing the boron-penetrating of effect in a CMOS transistor provides a silicon substrate, which comprises an isolating area, an active area and a gate oxide layer formed on the silicon substrate in the active layer. A polysilicon layer is then deposited on the silicon substrate. Next, boron ions (B+) are doped into the polysilicon layer. Next, a gate photoresist with a predetermined gate pattern is formed on the polysilicon layer. The polysilicon not covered by the gate photoresist is then etched to form a polysilicon gate. The gate photoresist is used as a mask to dope boron difluoride ions (BF2+) into the silicon substrate. Finally, after removing the gate photoresist, a tempering procedure is performed to form a shallow junction area of a source/drain region on the silicon substrate.

Abstract translation: 降低CMOS晶体管中的硼渗透的方法提供了一种硅衬底，其包括在有源层中的硅衬底上形成的隔离区，有源区和栅极氧化层。 然后在硅衬底上沉积多晶硅层。 接下来，将硼离子（B +）掺杂到多晶硅层中。 接下来，在多晶硅层上形成具有预定栅极图案的栅极光致抗蚀剂。 然后蚀刻未被栅极光致抗蚀剂覆盖的多晶硅以形成多晶硅栅极。 栅极光致抗蚀剂用作掩模以将二氟化硼离子（BF 2 +）掺杂到硅衬底中。 最后，在去除栅极光致抗蚀剂之后，进行回火处理以在硅衬底上形成源/漏区的浅结区。

公开(公告)号：US06432786B1

公开(公告)日：2002-08-13

申请号：US09829498

申请日：2001-04-09

Applicant: Chi-Chun Chen ,  Horng-Chih Lin ,  Chun-Yen Chang ,  Tiao-Yuan Huang

Inventor： Chi-Chun Chen ,  Horng-Chih Lin ,  Chun-Yen Chang ,  Tiao-Yuan Huang

IPC: H01L21425

Abstract: A method of forming a gate oxide layer with improved ability to resist process damage increases the reliability and yield of a transistor device. First, a nitrogen-containing gate oxide layer is formed on an element area of a silicon substrate. Then, a polysilicon layer is deposited on the gate oxide layer. Next, a gate doping process and a fluorine ion implantation are performed on the polysilicon layer. Then, a high-temperature tempering procedure is performed to make the fluorine enter the gate oxide layer.

公开(公告)号：US06232206B1

公开(公告)日：2001-05-15

申请号：US09208409

申请日：1998-12-10

Applicant: Tiao-Yuan Huang ,  Horng-Chih Lin

Inventor： Tiao-Yuan Huang ,  Horng-Chih Lin

IPC: H01L21425

CPC classification number: H01L27/0251 ,  Y10S438/966

Abstract: A method is provided for selective oxidation on source/drain regions of transistors on an integrated circuit. The method includes the steps of a) incorporating a neutral species into first kind of the source/drain regions, and b) forming oxidation regions over the first kind of source/drain regions and second kind of the source/drain regions, wherein the oxidation regions over the second kind are thicker than the oxidation regions over the first kind.

Abstract translation: 提供了一种用于在集成电路上的晶体管的源极/漏极区域上进行选择性氧化的方法。 该方法包括以下步骤：a）将中性物质并入第一种源极/漏极区域，以及b）在第一种源极/漏极区域和第二种源极/漏极区域上形成氧化区域，其中氧化 第二类的区域比第一类的氧化区域厚。

公开(公告)号：US5581105A

公开(公告)日：1996-12-03

申请号：US274928

申请日：1994-07-14

Applicant: Tiao-Yuan Huang

Inventor： Tiao-Yuan Huang

IPC: H01L27/02 ,  H01L29/78

CPC classification number: H01L27/0251 ,  H01L27/0266 ,  H01L27/0288 ,  Y10S148/136

Abstract: An input buffer for a CMOS integrated circuit comprises parallel pairs of complementary PMOS pull-up and NMOS pull-down transistors. For each NMOS transistor, a polysilicon NMOS gate lead structure includes three sections: a heavily doped gate section, an undoped resistor section, and a heavily doped contact section. The heavily doped contact section is contacted by a metal delivering a logic low voltage (V.sub.SS) so that the NMOS gate is resistively coupled to V.sub.SS. This resistance cooperates with the gate to drain resistance to define a voltage divider between V.sub.SS and V.sub.IN. This voltage divider leaves the gate at a small positive voltage during an electrostatic discharge event. This ensures that all NMOS transistors of a buffer become current bearing before any of them enters second breakdown. This arrangement maximizes input-buffer protection from electrostatic discharge events. The novel NMOS arrangement is readily compatible with CMOS fabrication techniques.

Abstract translation: 用于CMOS集成电路的输入缓冲器包括并行的互补PMOS上拉和NMOS下拉晶体管。 对于每个NMOS晶体管，多晶硅NMOS栅极引线结构包括三个部分：重掺杂栅极部分，未掺杂电阻部分和重掺杂接触部分。 重掺杂的接触部分由传递逻辑低电压（VSS）的金属接触，使得NMOS栅极电阻耦合到VSS。 该电阻与栅极配合以进行漏极电阻，以在VSS和VIN之间定义分压器。 这种分压器在静电放电事件期间以小的正电压离开栅极。 这确保了缓冲器的所有NMOS晶体管在其任何一个进入第二次击穿之前变为电流轴承。 这种布置使得输入缓冲器保护免受静电放电事件的影响。 该新颖的NMOS布置容易与CMOS制造技术兼容。

公开(公告)号：US4988638A

公开(公告)日：1991-01-29

申请号：US546288

申请日：1990-06-29

Applicant: Tiao-Yuan Huang ,  Anne Chiang ,  I-Wei Wu

Inventor： Tiao-Yuan Huang ,  Anne Chiang ,  I-Wei Wu

IPC: H01L27/092 ,  H01L29/786

CPC classification number: H01L27/1251 ,  H01L27/092 ,  H01L27/1214 ,  H01L29/78663 ,  H01L29/78672

Abstract: A thin film SOI CMOS device wherein the suitably doped deposited layers of an n-channel transistor and a p-channel transistor are simultaneously deposited. The source and drain elements of one transistor and the gate element of the other transistor are formed in a lower, highly doped, semiconductor layer and are separated from the corresponding gate element and source and drain elements formed in an upper, highly doped, semiconductor layer. The layer levels are separated by two intrinsic or lightly doped semiconductor layers sandwiching a dielectric layer, so that the intrinsic or lightly doped semiconductor layer lying contiguous to the source and drain elements serves as an active channel layer and the intrinsic or lightly doped semiconductor layer lying contiguous to the gate element serves to extend the gate layer.

Abstract translation: 一种薄膜SOI CMOS器件，其中同时沉积n沟道晶体管和p沟道晶体管的适当掺杂的沉积层。 一个晶体管的源极和漏极元件和另一个晶体管的栅极元件形成在下部，高度掺杂的半导体层中，并且与相应的栅极元件分离，并且源极和漏极元件形成在上部，高度掺杂的半导体层 。 层级由夹持介电层的两个本征或轻掺杂半导体层分开，使得邻近源极和漏极元件的本征或轻掺杂半导体层用作有源沟道层，并且本征或轻掺杂半导体层位于 邻接于栅极元件用于延伸栅极层。

公开(公告)号：US4907048A

公开(公告)日：1990-03-06

申请号：US123693

申请日：1987-11-23

Applicant: Tiao-Yuan Huang

Inventor： Tiao-Yuan Huang

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L29/7836 ,  H01L29/665 ,  H01L2924/0002 ,  Y10S257/90

Abstract: An improved double implanted and aligned LDD transistor comprising a gate having a central alignment member and a pair of outboard alignment members having portions contiguous with the gate oxide layer. A lightly doped junction is aligned with the central alignment members and a heavily doped junction is aligned with the outboard alignment members.

Abstract translation: 一种改进的双注入和对准LDD晶体管，其包括具有中心对准构件的栅极和具有与栅极氧化物层邻接的部分的一对外侧对准构件。 轻掺杂结与中心对准构件对准，并且重掺杂结与外侧对准构件对准。

公开(公告)号：US4907041A

公开(公告)日：1990-03-06

申请号：US245872

申请日：1988-09-16

Applicant: Tiao-Yuan Huang

Inventor： Tiao-Yuan Huang

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/6675 ,  H01L21/28273 ,  H01L29/7831 ,  H01L29/78645

Abstract: A high voltage thin film transistor comprising a substrate upon which is supported a non-single crystal semiconductor active layer, spaced from a pair of conductive gate electrodes by a gate dielectric layer, wherein one of the gate electrodes is the device control electrode and the other is a dummy-drain electrode. Heavily doped semiconductor source and drain electrodes are in substantially alignment with the outer edges of the gate electrodes, the source electrode being aligned with the device control electrode and the drain electrode being aligned with the dummy-drain electrode. The active layer has intrinsic or virtually intrinsic region thereof in opposition to the bodies of each of the gate electrodes, and an offset region, between the gate electrodes, having a lower dopant level than the source and drain electrodes, which is aligned with the inner edges of the gate electrodes.

公开(公告)号：US4904611A

公开(公告)日：1990-02-27

申请号：US277432

申请日：1988-11-25

Applicant: Anne Chiang ,  I-Wei Wu ,  Tiao-Yuan Huang

Inventor： Anne Chiang ,  I-Wei Wu ,  Tiao-Yuan Huang

IPC: H01L21/20

CPC classification number: H01L21/2022 ,  Y10S148/132

Abstract: A method of forming large grain polycrystalline films by deep ion implantation into a composite structure, comprising a layer of amorphous semiconductor material upon an insulating substrate. Implantation is of a given ion species at an implant energy and dosage sufficient to distrupt the interface between the amorphous layer and the substrate and to retard the process of nucleation in subsequent random crystallization upon thermal annealing.

Abstract translation: 通过深离子注入将大晶粒多晶膜形成复合结构的方法，其包括在绝缘基板上的非晶半导体材料层。 植入是一种给定的离子种类，其植入能量和剂量足以破坏非晶层和基底之间的界面，并且在热退火后的随后随机结晶中阻止成核过程。

公开(公告)号：US06894352B2

公开(公告)日：2005-05-17

申请号：US10602890

申请日：2003-06-25

Applicant: Shu-Fen Hu ,  Yung-Chun Wu ,  Wen-Tai Lu ,  Shiue-Shin Liu ,  Tiao-Yuan Huang ,  Tien-Sheng Chao

Inventor： Shu-Fen Hu ,  Yung-Chun Wu ,  Wen-Tai Lu ,  Shiue-Shin Liu ,  Tiao-Yuan Huang ,  Tien-Sheng Chao

IPC: H01L21/335 ,  H01L29/76 ,  H01L27/01

CPC classification number: B82Y10/00 ,  H01L29/66439 ,  H01L29/7613 ,  Y10S438/947 ,  Y10S977/937

Abstract: A method for fabricating a single-electron transistor (SET). A one dimensional channel is formed between source and drain on a silicon-on-insulator substrate, and the separated polysilicon sidewall spacer gates are formed by electron-beam lithographically etching process in a self-aligned manner. Operation of the single-electron transistor with self-aligned polysilicon sidewall spacer gates is achieved by applying external bias to the self-aligned polysilicon sidewall spacer gates to form two potential barriers and a quantum dot capable of storage charges between the two potential barriers. A metal upper gate is finally formed and biased to induce a two-dimensional electron gas (2DEG) and control the energy level of the quantum well. Accordingly, the method of the invention comprises a combination of electron beam (E-beam) lithography with multilayer-aligned direct writing technology, oxidation, and wet etching to form a nanoscale one-dimensional channel between source and drain on a silicon-on-insulator substrate.

Abstract translation: 一种用于制造单电子晶体管（SET）的方法。 在绝缘体上硅衬底上的源极和漏极之间形成一维沟道，并且以自对准方式通过电子束光刻蚀工艺形成分离的多晶硅侧壁间隔栅极。 通过将外部偏置施加到自对准多晶硅侧壁间隔栅上来形成具有自对准多晶硅侧壁间隔栅极的单电子晶体管的操作，以形成两个势垒和能够在两个势垒之间存储电荷的量子点。 金属上栅极最终形成并偏置以诱导二维电子气（2DEG）并控制量子阱的能级。 因此，本发明的方法包括电子束（E-beam）光刻与多层排列直接写入技术的组合，氧化和湿蚀刻，以在硅 - 硅上形成源极和漏极之间的纳米级一维沟道 绝缘体基板。

公开(公告)号：US5998246A

公开(公告)日：1999-12-07

申请号：US908721

申请日：1997-08-08

Applicant: Tiao-Yuan Huang ,  Horng-Chih Lin

Inventor： Tiao-Yuan Huang ,  Horng-Chih Lin

IPC: H01L21/336 ,  H01L29/786 ,  H01L21/00

CPC classification number: H01L29/66613 ,  H01L29/66765 ,  H01L29/78624 ,  H01L29/78678

Abstract: The present invention is related to a self-aligned manufacturing method of a thin film transistor for forming a single-crystal bottom-gate and an offset drain. The main object of the present invention is to disclose two manufacturing methods to attain the self-aligned manufacturing method of a thin film transistor for forming a single-crystal bottom-gate and an offset drain. In the first method, a photoresistor and a silicon nitride are used to form a dual stack as a mask, further a large-angle ion implant is used to form a thin film transistor with a single-crystal bottom-gate and an offset drain. In the second method, the source side is protected by a dual stack formed by a P+ polysilicon layer which may be discarded selectively and a silicon nitride and an insulation spacer of sidewall in order to selectively discard the silicon nitride on the drain side, thus the object of a thin film transistor with a single-crystal bottom-gate and an offset drain is obtained.

Abstract translation: 本发明涉及用于形成单晶底栅和偏移漏极的薄膜晶体管的自对准制造方法。 本发明的主要目的是公开用于形成单晶底栅和偏移漏极的薄膜晶体管的自对准制造方法的两种制造方法。 在第一种方法中，使用光敏电阻和氮化硅形成双重叠层作为掩模，此外，使用大角度离子注入来形成具有单晶底栅和偏移漏极的薄膜晶体管。 在第二种方法中，源极由可以被选择性地丢弃的P +多晶硅层和氮化硅和侧壁的绝缘间隔物形成的双重叠层保护，以便选择性地将漏极侧的氮化硅丢弃，因此， 获得具有单晶底栅和偏移漏极的薄膜晶体管的目的。