公开(公告)号：US09040986B2

公开(公告)日：2015-05-26

申请号：US13356243

申请日：2012-01-23

申请人： Ching-Fang Chen ,  Hsiang-Tai Lu ,  Chih-Hsien Lin

发明人： Ching-Fang Chen ,  Hsiang-Tai Lu ,  Chih-Hsien Lin

IPC分类号： H01L23/58 ,  H01L29/10 ,  H01L21/66 ,  H01L23/12 ,  H01L23/498 ,  H01L23/00

CPC分类号： G01R31/2886 ,  G01R31/2856 ,  H01L22/34 ,  H01L23/12 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01047

摘要： A three-dimensional integrated circuit (3DIC) including a top chip having at least one active device and an interposer having conductive routing layers and vias. The 3DIC further includes a plurality of conductive connectors configured to electrically connect the top chip and the interposer. The 3DIC further includes a conductive line over at least one of the top chip or the interposer. The conductive line traces a perimeter of top chip or interposer parallel to an outer edge of the top chip or interposer. The conductive line is configured to electrically connect the conductive connectors. The 3DIC further includes at least one testing element over at least one of the top chip or the interposer. The testing element is configured to electrically connect to the plurality of conductive connectors.

摘要翻译： 一种三维集成电路（3DIC），包括具有至少一个有源器件的顶部芯片和具有导电布线层和通孔的插入器。 3DIC还包括被配置为电连接顶部芯片和插入器的多个导电连接器。 3DIC还包括在顶部芯片或插入件中的至少一个上的导电线。 导线跟踪平行于顶部芯片或插入件的外边缘的顶部芯片或插入件的周边。 导线被配置为电连接导电连接器。 3DIC还包括至少一个测试元件在至少一个顶部芯片或插入器上。 测试元件被配置为电连接到多个导电连接器。

公开(公告)号：US20130248960A1

公开(公告)日：2013-09-26

申请号：US13425451

申请日：2012-03-21

申请人： Hsiang-Tai LU ,  Chih-Hsien LIN

发明人： Hsiang-Tai LU ,  Chih-Hsien LIN

IPC分类号： H01L29/788 ,  H01L21/66 ,  H01L21/336

CPC分类号： H01L27/11521 ,  G11C16/02 ,  G11C16/0416 ,  G11C16/225 ,  G11C29/04 ,  G11C2029/0403 ,  H01L21/28273 ,  H01L21/3205 ,  H01L22/14 ,  H01L27/11558

摘要： A semiconductor memory storage device includes first and second doped regions of a first type disposed in a semiconductor substrate. The first and second doped regions of the first type being laterally spaced from one another. A gate dielectric extends over the semiconductor substrate between the first and second doped regions, and a floating gate is disposed on the gate dielectric. An ultraviolet (UV) light blocking material is vertically disposed above the floating gate and has a size that covers the floating gate such that the floating gate remains electrically charged after the semiconductor memory storage device is exposed to UV light.

摘要翻译： 半导体存储器存储器件包括设置在半导体衬底中的第一类型的第一和第二掺杂区域。 第一类型的第一和第二掺杂区域彼此横向间隔开。 栅极电介质在第一和第二掺杂区域之间的半导体衬底上延伸，并且浮置栅极设置在栅极电介质上。 紫外（UV）遮光材料垂直地设置在浮动栅极上方，并且具有覆盖浮动栅极的尺寸，使得在半导体存储器存储装置暴露于紫外光之后浮置栅极保持充电。

公开(公告)号：US20130187156A1

公开(公告)日：2013-07-25

申请号：US13356243

申请日：2012-01-23

申请人： Ching-Fang CHEN ,  Hsiang-Tai LU ,  Chih-Hsien LIN

发明人： Ching-Fang CHEN ,  Hsiang-Tai LU ,  Chih-Hsien LIN

IPC分类号： H01L23/544 ,  H01L21/66

CPC分类号： G01R31/2886 ,  G01R31/2856 ,  H01L22/34 ,  H01L23/12 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01047

摘要： A three-dimensional integrated circuit (3DIC) including a top chip having at least one active device and an interposer having conductive routing layers and vias. The 3DIC further includes a plurality of conductive connectors configured to electrically connect the top chip and the interposer. The 3DIC further includes a conductive line over at least one of the top chip or the interposer. The conductive line traces a perimeter of top chip or interposer parallel to an outer edge of the top chip or interposer. The conductive line is configured to electrically connect the conductive connectors. The 3DIC further includes at least one testing element over at least one of the top chip or the interposer. The testing element is configured to electrically connect to the plurality of conductive connectors.

摘要翻译： 一种三维集成电路（3DIC），包括具有至少一个有源器件的顶部芯片和具有导电布线层和通孔的插入器。 3DIC还包括被配置为电连接顶部芯片和插入器的多个导电连接器。 3DIC还包括在顶部芯片或插入件中的至少一个上的导电线。 导线跟踪平行于顶部芯片或插入件的外边缘的顶部芯片或插入件的周边。 导线被配置为电连接导电连接器。 3DIC还包括至少一个测试元件在至少一个顶部芯片或插入器上。 测试元件被配置为电连接到多个导电连接器。

公开(公告)号：US20130026612A1

公开(公告)日：2013-01-31

申请号：US13194033

申请日：2011-07-29

申请人： Hsiang-Tai LU ,  Chih-Hsien LIN ,  Meng-Lin CHUNG

发明人： Hsiang-Tai LU ,  Chih-Hsien LIN ,  Meng-Lin CHUNG

IPC分类号： H01L23/552 ,  H01L21/265

CPC分类号： H01L21/265 ,  H01L21/76802 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/5225 ,  H01L23/552 ,  H01L2224/16

摘要： A passive interposer apparatus with a shielded through silicon via (TSV) configuration is disclosed. The apparatus includes a p-doped substrate, wherein at least an upper portion of the p-doped substrate is heavily p-doped. An interlayer dielectric layer (ILD) is disposed over the upper portion of the p-doped substrate. A plurality of through silicon vias (TSVs) are formed through the ILD and the p-doped substrate. A plurality of shielding lines disposed between the TSVs electrically couple respective second metal contact pads to the upper portion of the p-doped substrate.

摘要翻译： 公开了一种具有屏蔽硅通孔（TSV）配置的无源中介器。 该装置包括p掺杂衬底，其中至少p掺杂衬底的上部是高度p掺杂的。 层间电介质层（ILD）设置在p掺杂衬底的上部上。 通过ILD和p掺杂衬底形成多个穿通硅通孔（TSV）。 设置在TSV之间的多个屏蔽线将各个第二金属接触焊盘电耦合到p掺杂衬底的上部。

公开(公告)号：US20080024164A1

公开(公告)日：2008-01-31

申请号：US11496254

申请日：2006-07-31

申请人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

发明人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

IPC分类号： H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/1778

摘要： A system is disclosed for constructing a reconfigurable programmable logic device (PLD) comprising a first P-channel nonvolatile memory cell with a first source, a first drain and a first gate coupled to a first input node, a second P-channel nonvolatile memory cell with a second source, a second drain and a second gate coupled to a second input node, and an NMOS transistor with a third source and a third drain, wherein the first and second sources are commonly connected to a positive voltage supply (Vcc), the first, second and third drains are commonly connected to an output node and the third source is coupled to a complementary low voltage supply (Vss).

摘要翻译： 公开了一种用于构造可重构可编程逻辑器件（PLD）的系统，该可重构可编程逻辑器件（PLD）包括具有第一源极，第一漏极和耦合到第一输入节点的第一栅极的第一P沟道非易失性存储器单元，第二P沟道非易失性存储单元 具有第二源极，耦合到第二输入节点的第二漏极和第二栅极，以及具有第三源极和第三漏极的NMOS晶体管，其中所述第一和第二源极共同连接到正电压源（Vcc） 第一，第二和第三漏极通常连接到输出节点，并且第三源耦合到互补的低电压源（Vss）。

公开(公告)号：US20070296022A1

公开(公告)日：2007-12-27

申请号：US11848066

申请日：2007-08-30

申请人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Chin-Huang Wang

发明人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Chin-Huang Wang

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521

摘要： A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a substrate, and a poly silicon formed on the first insulating layer in the flash memory region. A mask layer is formed. Openings are formed in the flash memory region in the peripheral region. A local oxidation of silicon (LOCOS) is performed to form thick oxides on poly silicon, and a field oxide on silicon substrate respectively. The mask layer is removed. A control gate and a control gate oxide are formed on the thick oxide and the poly silicon. A gate electrode is formed with at least one end residing on a field oxide so that the resulting HV-LDMOS has a high breakdown voltage. Spacers and a source/drain of the flash cells and HV-LDMOSs are then formed.

摘要翻译： 提出了一种将诸如HV-LDMOS之类的外围设备的形成嵌入到闪速存储器的形成中的方法。 层叠结构形成有在基板上形成的第一绝缘层，以及形成在闪存区域中的第一绝缘层上的多晶硅。 形成掩模层。 开口形成在周边区域的闪存区域中。 进行硅的局部氧化（LOCOS）以在多晶硅上形成厚氧化物，分别在硅衬底上形成场氧化物。 去除掩模层。 在厚氧化物和多晶硅上形成控制栅极和控制栅极氧化物。 栅电极形成有驻留在场氧化物上的至少一端，使得所得的HV-LDMOS具有高的击穿电压。 然后形成闪存单元和HV-LDMOS的间隔物和源极/漏极。

公开(公告)号：US06958939B2

公开(公告)日：2005-10-25

申请号：US10663425

申请日：2003-09-15

申请人： Chia-Ta Hsieh ,  Chin-Huang Wang ,  I-Ming Chang ,  Hsiang-Tai Lu

发明人： Chia-Ta Hsieh ,  Chin-Huang Wang ,  I-Ming Chang ,  Hsiang-Tai Lu

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： G11C16/0425 ,  G11C16/0466 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7885

摘要： A flash memory cell of an EEPROM split-gate flash memory, the memory cell including a substrate having a plurality of active regions, and a floating gate structure disposed over the substrate. The floating gate structure extends across at least three of the active regions of the substrate such that the floating gate structure and the at least three active regions define at least two channel regions dedicated for programming.

摘要翻译： EEPROM分离栅闪存的快闪存储器单元，该存储单元包括具有多个有源区的衬底，以及设置在衬底上的浮栅结构。 浮置栅极结构延伸穿过衬底的有源区域中的至少三个，使得浮动栅极结构和至少三个有源区域限定专用于编程的至少两个沟道区域。

公开(公告)号：US20050057971A1

公开(公告)日：2005-03-17

申请号：US10663425

申请日：2003-09-15

申请人： Chia-Ta Hsieh ,  Chin-Huang Wang ,  I-Ming Chang ,  Hsiang-Tai Lu

发明人： Chia-Ta Hsieh ,  Chin-Huang Wang ,  I-Ming Chang ,  Hsiang-Tai Lu

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： G11C16/0425 ,  G11C16/0466 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7885

摘要： A flash memory cell of an EEPROM split-gate flash memory, the memory cell including a substrate having a plurality of active regions, and a floating gate structure disposed over the substrate. The floating gate structure extends across at least three of the active regions of the substrate such that the floating gate structure and the at least three active regions define at least two channel regions dedicated for programming.

公开(公告)号：US08618640B2

公开(公告)日：2013-12-31

申请号：US13194033

申请日：2011-07-29

申请人： Hsiang-Tai Lu ,  Chih-Hsien Lin ,  Meng-Lin Chung

发明人： Hsiang-Tai Lu ,  Chih-Hsien Lin ,  Meng-Lin Chung

IPC分类号： H01L23/552

CPC分类号： H01L21/265 ,  H01L21/76802 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/5225 ,  H01L23/552 ,  H01L2224/16

摘要： A passive interposer apparatus with a shielded through silicon via (TSV) configuration is disclosed. The apparatus includes a p-doped substrate, wherein at least an upper portion of the p-doped substrate is heavily p-doped. An interlayer dielectric layer (ILD) is disposed over the upper portion of the p-doped substrate. A plurality of through silicon vias (TSVs) are formed through the ILD and the p-doped substrate. A plurality of shielding lines disposed between the TSVs electrically couple respective second metal contact pads to the upper portion of the p-doped substrate.

摘要翻译： 公开了一种具有屏蔽硅通孔（TSV）配置的无源中介器。 该装置包括p掺杂衬底，其中至少p掺杂衬底的上部是高度p掺杂的。 层间电介质层（ILD）设置在p掺杂衬底的上部上。 通过ILD和p掺杂衬底形成多个穿通硅通孔（TSV）。 设置在TSV之间的多个屏蔽线将各个第二金属接触焊盘电耦合到p掺杂衬底的上部。

公开(公告)号：US07462906B2

公开(公告)日：2008-12-09

申请号：US11848066

申请日：2007-08-30

申请人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Chin-Huang Wang

发明人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Chin-Huang Wang

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521

摘要： A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a substrate, and a poly silicon formed on the first insulating layer in the flash memory region. A mask layer is formed. Openings are formed in the flash memory region in the peripheral region. A local oxidation of silicon (LOCOS) is performed to form thick oxides on poly silicon, and a field oxide on silicon substrate respectively. The mask layer is removed. A control gate and a control gate oxide are formed on the thick oxide and the poly silicon. A gate electrode is formed with at least one end residing on a field oxide so that the resulting HV-LDMOS has a high breakdown voltage. Spacers and a source/drain of the flash cells and HV-LDMOSs are then formed.

摘要翻译： 提出了一种将诸如HV-LDMOS之类的外围设备的形成嵌入到闪速存储器的形成中的方法。 层叠结构形成有在基板上形成的第一绝缘层，以及形成在闪存区域中的第一绝缘层上的多晶硅。 形成掩模层。 开口形成在周边区域的闪存区域中。 进行硅的局部氧化（LOCOS）以在多晶硅上形成厚氧化物，分别在硅衬底上形成场氧化物。 去除掩模层。 在厚氧化物和多晶硅上形成控制栅极和控制栅极氧化物。 栅电极形成有驻留在场氧化物上的至少一端，使得所得的HV-LDMOS具有高的击穿电压。 然后形成闪存单元和HV-LDMOS的间隔物和源极/漏极。