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    SYNERGIST FOR IMPROVING CROP STRESS RESISTANCE AND FERTILIZER ABSORPTION CAPACITY
    2.
    发明申请
    SYNERGIST FOR IMPROVING CROP STRESS RESISTANCE AND FERTILIZER ABSORPTION CAPACITY 审中-公开

    公开(公告)号：US20200170260A1

    公开(公告)日：2020-06-04

    申请号：US16699513

    申请日：2019-11-29

    Applicant: SICHUAN HUI TAI AGRICULTURAL TECHNOLOGY CO. LTD.

    Inventor： Lezhang CHEN ,  Junbo YANG

    IPC: A01N65/26 ,  A01N59/16 ,  A01N59/06 ,  A01N25/12 ,  C05G3/00 ,  A01N63/00

    Abstract: The invention discloses a synergist for improving crop resistance and fertilizer absorption capacity. The synergist includes the following components by weight: 20-30 parts of an oyster shell powder, 20-30 parts of a water chestnut skin powder, 10-20 parts of a chinaberry bark powder, 10-20 parts of a magnetic material, 10-20 parts of an illite powder, 5-10 parts of a shiitake mushroom polysaccharide extract. The synergist can, on one hand, improve the resistance of crops, especially reducing the pests and diseases significantly, improving waterlogging and drought resistance; and, on the other hand, greatly reduce the use of fertilizers, especially nitrogen fertilizers, preventing soil compaction. It can also significantly increase the content of active polysaccharides, especially β-glucan in crops. In addition, the raw materials are readily available, the cost is low, and there are significant economic benefits.

    Integrated circuit design using DFM-enhanced architecture
    3.
    发明授权
    Integrated circuit design using DFM-enhanced architecture 有权
    采用DFM增强架构的集成电路设计

    公开(公告)号：US08631366B2

    公开(公告)日：2014-01-14

    申请号：US12708242

    申请日：2010-02-18

    Applicant: Yung-Chin Hou ,  Lee-Chung Lu ,  Li-Chun Tien ,  Yi-Kan Cheng ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Yuan-Te Hou

    Inventor： Yung-Chin Hou ,  Lee-Chung Lu ,  Li-Chun Tien ,  Yi-Kan Cheng ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Yuan-Te Hou

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    Abstract: Integrated circuit libraries include a first standard cell having a first left boundary and a first right boundary, and a second standard cell having a second left boundary and a second right boundary. The first standard cell and the second standard cell are of a same cell variant. A first active region in the first standard cell has a different length of diffusion than a second active region in the second standard cell. The first active region and the second active region are corresponding active regions represented by a same component of a same circuit diagram representing both the first standard cell and the second standard cell.

    Abstract translation: 集成电路库包括具有第一左边界和第一右边界的第一标准单元，以及具有第二左边界和第二右边界的第二标准单元。 第一标准细胞和第二标准细胞具有相同的细胞变体。 第一标准单元中的第一有源区具有与第二标准单元中的第二有源区不同的扩散长度。 第一有源区和第二有源区是由表示第一标准单元和第二标准单元的相同电路图的相同分量表示的相应有源区。

    Standard Cell without OD Space Effect in Y-Direction
    4.
    发明申请
    Standard Cell without OD Space Effect in Y-Direction 有权
    标准电池在Y方向没有OD空间效应

    公开(公告)号：US20100078725A1

    公开(公告)日：2010-04-01

    申请号：US12345372

    申请日：2008-12-29

    Applicant: Yung-Chin Hou ,  Lee-Chung Lu ,  Ta-Pen Guo ,  Li-Chun Tien ,  Ping Chung Li ,  Chun-Hui Tai ,  Shu-Min Chen

    Inventor： Yung-Chin Hou ,  Lee-Chung Lu ,  Ta-Pen Guo ,  Li-Chun Tien ,  Ping Chung Li ,  Chun-Hui Tai ,  Shu-Min Chen

    IPC: H01L27/088 ,  H01L29/06

    CPC classification number: H01L27/0207 ,  H01L27/11807

    Abstract: An integrated circuit structure includes a semiconductor substrate; a first active region in the semiconductor substrate; and a second active region in the semiconductor substrate and of an opposite conductivity type than the first active region. A gate electrode strip is over the first and the second active regions and forms a first MOS device and a second MOS device with the first active region and the second active region, respectively. A first spacer bar is in the semiconductor substrate and connected to the first active region. At least a portion of the first spacer bar is adjacent to and spaced apart from a portion of the first active region. A second spacer bar is in the semiconductor substrate and connected to the second active region. At least a portion of the second spacer bar is adjacent to and spaced apart from a portion of the second active region.

    Abstract translation: 集成电路结构包括半导体衬底; 半导体衬底中的第一有源区; 以及在所述半导体衬底中并且具有与所述第一有源区相反的导电类型的第二有源区。 栅电极条在第一和第二有源区之上，分别形成具有第一有源区和第二有源区的第一MOS器件和第二MOS器件。 第一间隔棒位于半导体衬底中并与第一有源区连接。 第一间隔条的至少一部分与第一有源区的一部分相邻并间隔开。 第二间隔杆位于半导体衬底中并连接到第二有源区。 第二间隔杆的至少一部分与第二有源区的一部分相邻并间隔开。

    Mother/daughter switch design with self power-up control
    5.
    发明申请
    Mother/daughter switch design with self power-up control 有权
    母/子开关设计具有自上电控制功能

    公开(公告)号：US20080270813A1

    公开(公告)日：2008-10-30

    申请号：US11789721

    申请日：2007-04-24

    Applicant: Shih-Hsien Yang ,  Chung-Hsing Wang ,  Lee-Chung Lu ,  Chun-Hui Tai ,  Cliff Hou

    Inventor： Shih-Hsien Yang ,  Chung-Hsing Wang ,  Lee-Chung Lu ,  Chun-Hui Tai ,  Cliff Hou

    IPC: G06F1/32

    CPC classification number: G06F1/3203

    Abstract: System and method for providing power to integrated circuitry with good power-on responsive time and reduced power-on transient glitches. A preferred embodiment comprises a daughter switch coupled to a circuit block, a first control circuit coupled to the daughter circuit, a second control circuit coupled to the first control circuit, and a mother circuit coupled to the circuit block and to the second control circuit. After the daughter switch is turned on by a control signal, the mother switch is not turned on until the daughter switch has discharged (charged) the voltage potential across power rails of the mother circuit to a point where glitches are minimized. The second control circuit turns on the mother circuit when the reduced voltage potential is reached, with a signal produced by the first control circuit reflects the voltage potential. Furthermore, a bypass circuit can be used to reduce leakage current.

    Abstract translation: 为集成电路提供电源的系统和方法具有良好的上电响应时间和减少的上电瞬态毛刺。 优选实施例包括耦合到电路块的子开关，耦合到子电路的第一控制电路，耦合到第一控制电路的第二控制电路以及耦合到电路块和第二控制电路的母电路。 在通过控制信号接通子开关之后，母开关直到子开关已经将母电路的电源轨上的电压放电（充电）到毛刺最小化的位置为止。 当达到降低的电压电位时，第二控制电路接通母电路，由第一控制电路产生的信号反映电压电位。 此外，可以使用旁路电路来减少泄漏电流。

    Heat-resistant lens kit
    6.
    发明申请
    Heat-resistant lens kit 失效
    耐热镜片套件

    公开(公告)号：US20080211527A1

    公开(公告)日：2008-09-04

    申请号：US11819083

    申请日：2007-06-25

    Applicant: Pi-Hui Tai

    Inventor： Pi-Hui Tai

    IPC: G01R31/308

    CPC classification number: G01R31/2874

    Abstract: A heat-resistant lens kit configured within the pogo tower of the wafer tester is disclosed. The heat-resistant lens kit has two parallel lenses and a main body with a through hole. The main body and two parallel lenses enclose a vacuum room within the through hole.

    Abstract translation: 公开了一种配置在晶片测试器的波峰塔内的耐热透镜套件。 耐热透镜套件具有两个平行透镜和具有通孔的主体。 主体和两个平行透镜在通孔内包围一个真空室。

    Reverse-biased PN diode decoupling capacitor
    7.
    发明申请
    Reverse-biased PN diode decoupling capacitor 有权
    反向偏置PN二极管去耦电容

    公开(公告)号：US20080122036A1

    公开(公告)日：2008-05-29

    申请号：US11502094

    申请日：2006-08-10

    Applicant: Hsien-Te Chen ,  Jen-Hang Yang ,  Chun-Hui Tai

    Inventor： Hsien-Te Chen ,  Jen-Hang Yang ,  Chun-Hui Tai

    IPC: H01L29/93

    CPC classification number: H01L29/8611 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0814

    Abstract: This invention discloses a decoupling capacitor in an integrated circuit, comprising a plurality of dedicated PN diodes with a total junction area greater than one tenth of a total active area of functional devices for which the dedicated PN diodes are intended to protect, a N-type region of the dedicated PN diodes coupling to a positive supply voltage (Vdd), and a P-type region of the dedicated PN diodes coupling to a complimentary lower supply voltage (Vss), wherein the dedicated PN diodes are reversely biased.

    Abstract translation: 本发明公开了一种集成电路中的去耦电容器，其包括多个专用PN二极管，其总结面积大于专用PN二极管旨在保护的功能器件的总有效面积的十分之一，N型 耦合到正电源电压（Vdd）的专用PN二极管的区域和耦合到互补的较低电源电压（Vss）的专用PN二极管的P型区域，其中专用PN二极管被反向偏置。

    Portable blackbody furnace
    8.
    发明申请
    Portable blackbody furnace 有权
    便携式黑体炉

    公开(公告)号：US20060081598A1

    公开(公告)日：2006-04-20

    申请号：US11250386

    申请日：2005-10-17

    Applicant: John Lin ,  Chau Chen ,  Chun Hsu ,  Hui Tai ,  Hsin Ko ,  Chun Lin ,  Chuen Liou

    Inventor： John Lin ,  Chau Chen ,  Chun Hsu ,  Hui Tai ,  Hsin Ko ,  Chun Lin ,  Chuen Liou

    IPC: F27B14/00

    CPC classification number: F27B17/0016 ,  F27D19/00 ,  F27D21/0014

    Abstract: The present invention discloses a portable blackbody furnace comprising a metallic body, a cylindrical cavity with a tapered end in the metallic body, a shielding plate positioned at an open end of the cylindrical cavity, at least a first heaters positioned in the shielding plate, a plurality of second heaters positioned around the metallic body, and a plurality of thermometers positioned in the metallic body. Preferably, the heat capacity of the metallic body is larger than 200 Joules/K, and has radial thickness larger than 5 mm. There are grooves formed on the outer wall of the metallic body, and the second heaters are heating wires embedded inside the grooves. In addition, the flow direction of the current between two adjacent heating wires is opposite to eliminate the magnetic field generated from the current flow.

    Abstract translation: 本发明公开了一种便携式黑体炉，它包括金属体，在金属体中具有锥形端的圆柱形空腔，位于圆柱形空腔的开口端的屏蔽板，至少位于屏蔽板中的第一加热器， 围绕金属体定位的多个第二加热器和位于金属体中的多个温度计。 优选地，金属体的热容量大于200焦耳/ K，并且径向厚度大于5mm。 在金属体的外壁上形成有凹槽，第二加热器是嵌入槽内的加热丝。 此外，两个相邻加热丝之间的电流的流动方向是相反的，以消除由电流产生的磁场。

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