-
公开(公告)号：US20120008416A1
公开(公告)日：2012-01-12
申请号：US13177764
申请日：2011-07-07
Applicant: Myung CHO , Hwang HUH , Jung Hwan LEE , Ji Hwan KIM
Inventor： Myung CHO , Hwang HUH , Jung Hwan LEE , Ji Hwan KIM
CPC classification number: G11C16/26 , G11C16/10 , G11C29/1201 , G11C29/50 , G11C2029/5006 , G11C2216/14
Abstract: A semiconductor memory device includes a memory cell array comprising a plurality of cell strings and a page buffer group comprising a plurality of page buffers coupled to the respective cell string through bit lines. Each of the page buffers includes a latch unit for storing data to be programmed into memory cells included in the cell string or for storing data read from the memory cells. Each of the page buffers is coupled to a pad for the test operation of the memory cells according to data stored in the latch unit in the test operation.
Abstract translation: 半导体存储器件包括包括多个单元串的存储单元阵列和包括通过位线耦合到各个单元串的多个页缓冲器的页缓冲器组。 每个页面缓冲器包括用于存储要被编程到包括在单元串中的存储器单元中的数据或用于存储从存储器单元读取的数据的锁存单元。 根据在测试操作中存储在锁存单元中的数据，每个页缓冲器被耦合到用于存储器单元的测试操作的焊盘。
-
公开(公告)号：US20100195386A1
公开(公告)日：2010-08-05
申请号：US12650766
申请日：2009-12-31
Applicant: Hwang Huh
Inventor： Hwang Huh
CPC classification number: G11C16/0483 , G11C16/26 , G11C16/3454
Abstract: A page buffer circuit comprises a sense amplification unit configured to compare a reference voltage and a bit line voltage of a bit line of a selected memory block and to increase a voltage level of a sense node by a difference between the reference voltage and the bit line voltage, wherein the bit line voltage is subject to being changed according to a program state of a selected memory, and a number of latch circuits configured to latch program verification data according to the voltage level of the sense node.
Abstract translation: 页面缓冲电路包括读出放大单元，其被配置为比较所选存储块的位线的参考电压和位线电压，并且通过参考电压和位线之间的差来增加感测节点的电压电平 电压，其中所述位线电压根据所选存储器的编程状态而被改变，并且多个锁存电路被配置为根据所述感测节点的电压电平来锁存程序验证数据。
-
公开(公告)号：US08582367B2
公开(公告)日：2013-11-12
申请号：US13177764
申请日：2011-07-07
Applicant: Myung Cho , Hwang Huh , Jung Hwan Lee , Ji Hwan Kim
Inventor： Myung Cho , Hwang Huh , Jung Hwan Lee , Ji Hwan Kim
CPC classification number: G11C16/26 , G11C16/10 , G11C29/1201 , G11C29/50 , G11C2029/5006 , G11C2216/14
Abstract: A semiconductor memory device includes a memory cell array comprising a plurality of cell strings and a page buffer group comprising a plurality of page buffers coupled to the respective cell string through bit lines. Each of the page buffers includes a latch unit for storing data to be programmed into memory cells included in the cell string or for storing data read from the memory cells. Each of the page buffers is coupled to a pad for the test operation of the memory cells according to data stored in the latch unit in the test operation.
Abstract translation: 半导体存储器件包括包括多个单元串的存储单元阵列和包括通过位线耦合到各个单元串的多个页缓冲器的页缓冲器组。 每个页面缓冲器包括用于存储要被编程到包括在单元串中的存储器单元中的数据或用于存储从存储器单元读取的数据的锁存单元。 根据在测试操作中存储在锁存单元中的数据，每个页缓冲器被耦合到用于存储器单元的测试操作的焊盘。
-
4.发明授权Page buffer of nonvolatile memory device and method of performing program verification operation using the same 有权非易失性存储器件的页面缓冲器和使用其执行程序验证操作的方法公开(公告)号：US08194464B2
公开(公告)日：2012-06-05
申请号：US12764331
申请日：2010-04-21
IPC: G11C11/34
CPC classification number: G11C11/5628 , G11C16/10 , G11C2211/5621
Abstract: A page buffer of a nonvolatile memory device comprises a sense unit coupled between the sense node and the bit lines of a memory cell array, comprising a number of memory cells, and configured to precharge the bit lines to different voltage levels in response to a page buffer sense signal of a first or second voltage level, a MUX unit configured to output the page buffer sense signal of the first or second voltage level in response to a control signal according to a value of program data, a flag latch configured to temporarily store the program data and to output the control signal to the MUX unit, and a main latch configured to sense the voltage levels of the bit lines via the sense node and to perform a program verification operation.
Abstract translation: 非易失性存储器件的页面缓冲器包括耦合在感测节点和存储器单元阵列的位线之间的感测单元，其包括多个存储器单元，并且被配置为响应于页面将位线预充电到不同的电压电平 第一或第二电压电平的缓冲器检测信号，MUX单元，被配置为响应于根据节目数据的值的控制信号输出第一或第二电压电平的寻呼缓冲器感测信号;配置为临时存储的标志锁存器 所述程序数据并将所述控制信号输出到所述MUX单元，以及主锁存器，被配置为经由所述感测节点感测所述位线的电压电平并执行程序验证操作。
-
5.发明申请公开(公告)号：US20130208538A1
公开(公告)日：2013-08-15
申请号：US13584990
申请日：2012-08-14
Applicant: Chang Won YANG , Hwang HUH
Inventor： Chang Won YANG , Hwang HUH
IPC: G11C16/28
Abstract: A nonvolatile semiconductor memory apparatus includes a memory cell block, a plurality of page buffers, and a reference page buffer unit. The memory cell block includes a plurality of memory cell strings each of which includes a plurality of memory cells and a dummy memory cell string which includes a plurality of dummy memory cells. The page buffers sense data stored in the memory cells and apply the sensed data to an output node. The reference page buffer unit senses the dummy memory cells and adjusts the timing to apply the values sensed by the page buffers to the output node.
Abstract translation: 非易失性半导体存储装置包括存储单元块，多个页缓冲器和参考页缓冲单元。 存储单元块包括多个存储单元串，每个存储单元串包括多个存储单元和包括多个虚拟存储单元的虚拟存储单元串。 页缓冲器感测存储在存储单元中的数据，并将感测数据应用于输出节点。 参考页面缓冲器单元感测虚拟存储器单元并且调整定时以将由页面缓冲器感测的值应用于输出节点。
-
Patent Agency Ranking
公开(公告)号：US08179722B2
公开(公告)日：2012-05-15
申请号：US12650766
申请日：2009-12-31
Applicant: Hwang Huh
Inventor： Hwang Huh
IPC: G11C16/06
CPC classification number: G11C16/0483 , G11C16/26 , G11C16/3454
Abstract: A page buffer circuit comprises a sense amplification unit configured to compare a reference voltage and a bit line voltage of a bit line of a selected memory block and to increase a voltage level of a sense node by a difference between the reference voltage and the bit line voltage, wherein the bit line voltage is subject to being changed according to a program state of a selected memory, and a number of latch circuits configured to latch program verification data according to the voltage level of the sense node.
Abstract translation: 页面缓冲电路包括读出放大单元，其被配置为比较所选存储块的位线的参考电压和位线电压，并且通过参考电压和位线之间的差来增加感测节点的电压电平 电压，其中所述位线电压根据所选存储器的编程状态而被改变，并且多个锁存电路被配置为根据所述感测节点的电压电平来锁存程序验证数据。
-
7.发明申请PAGE BUFFER CIRCUIT, NONVOLATILE MEMORY DEVICE INCLUDING THE PAGE BUFFER CIRCUIT, AND METHOD OF OPERATING THE NONVOLATILE MEMORY DEVICE 有权页面缓冲器电路，包括页面缓冲器电路的非易失性存储器件以及操作非易失性存储器件的方法公开(公告)号：US20100309725A1
公开(公告)日：2010-12-09
申请号：US12780140
申请日：2010-05-14
Applicant: Hwang Huh
Inventor： Hwang Huh
CPC classification number: G11C16/06 , G11C7/1039
Abstract: A page buffer circuit including a bit line selection unit configured to select the first or second bit line in response to a first control signal and couple the selected bit line to a sense node, or to selectively precharge or discharge the first and second bit lines to a first voltage level, a first latch unit configured to store program data and output the stored program data to the sense node, a second latch unit configured to store data of a low logic level in response to a reset signal and discharge a selected bit line from a precharge state to a second voltage level, and a voltage control element configured to raise a voltage level of the sense node or drop a voltage level of the sense node to a third voltage level in response to a second control signal.
Abstract translation: 一种页缓冲电路，包括位线选择单元，配置为响应于第一控制信号选择第一位线或第二位线，并将所选位线耦合到感测节点，或选择性地将第一和第二位线预充电或放电至 第一电压电平，第一锁存单元，被配置为存储程序数据并将存储的程序数据输出到感测节点;第二锁存单元，被配置为响应于复位信号存储低逻辑电平的数据，并且将所选择的位线 以及电压控制元件，其被配置为响应于第二控制信号而升高感测节点的电压电平或将感测节点的电压电平降低到第三电压电平。
-
8.发明授权公开(公告)号：US09093169B2
公开(公告)日：2015-07-28
申请号：US13584990
申请日：2012-08-14
Applicant: Chang Won Yang , Hwang Huh
Inventor： Chang Won Yang , Hwang Huh
Abstract: A nonvolatile semiconductor memory apparatus includes a memory cell block, a plurality of page buffers, and a reference page buffer unit. The memory cell block includes a plurality of memory cell strings each of which includes a plurality of memory cells and a dummy memory cell string which includes a plurality of dummy memory cells. The page buffers sense data stored in the memory cells and apply the sensed data to an output node. The reference page buffer unit senses the dummy memory cells and adjusts the timing to apply the values sensed by the page buffers to the output node.
Abstract translation: 非易失性半导体存储装置包括存储单元块，多个页缓冲器和参考页缓冲单元。 存储单元块包括多个存储单元串，每个存储单元串包括多个存储单元和包括多个虚拟存储单元的虚拟存储单元串。 页缓冲器感测存储在存储单元中的数据，并将感测数据应用于输出节点。 参考页面缓冲器单元感测虚拟存储器单元并且调整定时以将由页面缓冲器感测的值应用于输出节点。
-
公开(公告)号：US08913427B2
公开(公告)日：2014-12-16
申请号：US13602008
申请日：2012-08-31
Applicant: Hwang Huh
Inventor： Hwang Huh
IPC: G11C11/34
Abstract: A semiconductor memory device of the present invention includes a memory cell array with cell strings having word lines stacked on a substrate and a vertical channel layer formed through the word lines, a peripheral circuit configured to select one of the word lines and perform a program operation on the selected word line, and a control circuit configured to control the peripheral circuit to perform the program operation by applying a program voltage to a word line selected for the program operation, applying a ground voltage to a word line of which a program operation has been completed and applying a pass voltage to the other word lines.
Abstract translation: 本发明的半导体存储器件包括具有堆叠在基板上的字线的单元串和通过字线形成的垂直沟道层的存储单元阵列，外围电路被配置为选择一个字线并执行编程操作 以及控制电路，被配置为通过将程序电压施加到为编程操作选择的字线来控制外围电路来执行编程操作，将接地电压施加到程序操作具有的字线 已经完成并对其他字线施加通过电压。
-
公开(公告)号：US08582368B2
公开(公告)日：2013-11-12
申请号：US12833582
申请日：2010-07-09
Applicant: Hwang Huh , Seong-Je Park
Inventor： Hwang Huh , Seong-Je Park
IPC: G11C11/34
CPC classification number: G11C16/3459 , G11C7/04 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C2211/5621 , G11C2211/5642
Abstract: A method for operating a non-volatile memory device includes counting the number of consecutive verify operations performed without a precharge, sensing a temperature, and when the number of verify operations exceeds a set value of verify operations, controlling a level of a sensing bias voltage based on the sensed temperature.
Abstract translation: 一种用于操作非易失性存储器件的方法包括对没有预充电，感测温度进行的连续验证操作的数量进行计数，以及当验证操作次数超过验证操作的设定值时，控制感测偏置电压的电平 基于感测到的温度。
-
-
-
-
-
-
-
-
-
Search Results
19
records
(took 0.01 seconds)
