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公开(公告)号：US20130070512A1
公开(公告)日：2013-03-21
申请号：US13340074
申请日：2011-12-29
申请人： Hyuck-Sang Yim , Kwang-Seok Kim , Taek-Sang Song , Chul-Hyun Park
发明人： Hyuck-Sang Yim , Kwang-Seok Kim , Taek-Sang Song , Chul-Hyun Park
IPC分类号： G11C11/00
CPC分类号： G11C5/147 , G11C13/0004 , G11C13/004 , G11C2013/0054
摘要： A non-volatile memory device includes a memory cell including a resistance variable device and a switching unit for controlling a current flowing through the resistance variable device; a read reference voltage generator configured to generate a reference voltage according to a skew occurring in the switching unit; and a sense amplifier configured to sense a voltage corresponding to the current that flows through the resistance variable device based on the reference voltage.
摘要翻译： 非易失性存储器件包括：存储单元，包括电阻可变器件和用于控制流过电阻可变器件的电流的开关单元; 读取参考电压发生器，被配置为根据在所述开关单元中发生的偏斜产生参考电压; 以及感测放大器，被配置为基于所述参考电压来感测对应于流过所述电阻可变器件的电流的电压。
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公开(公告)号：US09741434B2
公开(公告)日：2017-08-22
申请号：US14018287
申请日：2013-09-04
申请人： Akira Katayama , Masahiro Takahashi , Tsuneo Inaba , Hyuck Sang Yim , Dong Keun Kim , Byoung Chan Oh , Ji Wang Lee
发明人： Akira Katayama , Masahiro Takahashi , Tsuneo Inaba , Hyuck Sang Yim , Dong Keun Kim , Byoung Chan Oh , Ji Wang Lee
CPC分类号： G11C13/004 , G11C5/06 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C2013/0054
摘要： According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.
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公开(公告)号：US09336871B2
公开(公告)日：2016-05-10
申请号：US14811237
申请日：2015-07-28
CPC分类号： G11C13/003 , G11C11/1659 , G11C11/1673 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C2013/0054
摘要： According to one embodiment, a resistance change memory includes the following configuration. A first inverter includes first input and first output terminals and first and second voltage terminals. A second inverter includes second input and second output terminals and third and fourth voltage terminals. The second input terminal is connected to the first output terminal. The second output terminal is connected to the first input terminal. First and second transistors are connected to the first and second output terminals, respectively. Third and fourth transistors are connected to the first and third voltage terminals, respectively. A fifth transistor is connected between the first voltage terminal and the first memory cell. A sixth transistor is connected to the third voltage terminal. A controller turns on the first and second transistors, after turning off the fifth and sixth transistors.
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公开(公告)号：US20150340087A1
公开(公告)日：2015-11-26
申请号：US14811237
申请日：2015-07-28
CPC分类号： G11C13/003 , G11C11/1659 , G11C11/1673 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C2013/0054
摘要： According to one embodiment, a resistance change memory includes the following configuration. A first inverter includes first input and first output terminals and first and second voltage terminals. A second inverter includes second input and second output terminals and third and fourth voltage terminals. The second input terminal is connected to the first output terminal. The second output terminal is connected to the first input terminal. First and second transistors are connected to the first and second output terminals, respectively. Third and fourth transistors are connected to the first and third voltage terminals, respectively. A fifth transistor is connected between the first voltage terminal and the first memory cell. A sixth transistor is connected to the third voltage terminal. A controller turns on the first and second transistors, after turning off the fifth and sixth transistors.
摘要翻译： 根据一个实施例，电阻变化存储器包括以下配置。 第一反相器包括第一输入端和第一输出端以及第一和第二电压端。 第二反相器包括第二输入端和第二输出端以及第三和第四电压端。 第二输入端子连接到第一输出端子。 第二输出端子连接到第一输入端子。 第一和第二晶体管分别连接到第一和第二输出端子。 第三和第四晶体管分别连接到第一和第三电压端子。 第五晶体管连接在第一电压端和第一存储单元之间。 第六晶体管连接到第三电压端子。 在关闭第五和第六晶体管之后，控制器接通第一和第二晶体管。
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公开(公告)号：US08659930B2
公开(公告)日：2014-02-25
申请号：US13340074
申请日：2011-12-29
申请人： Hyuck-Sang Yim , Kwang-Seok Kim , Taek-Sang Song , Chul-Hyun Park
发明人： Hyuck-Sang Yim , Kwang-Seok Kim , Taek-Sang Song , Chul-Hyun Park
IPC分类号： G11C11/00
CPC分类号： G11C5/147 , G11C13/0004 , G11C13/004 , G11C2013/0054
摘要： A non-volatile memory device includes a memory cell including a resistance variable device and a switching unit for controlling a current flowing through the resistance variable device; a read reference voltage generator configured to generate a reference voltage according to a skew occurring in the switching unit; and a sense amplifier configured to sense a voltage corresponding to the current that flows through the resistance variable device based on the reference voltage.
摘要翻译： 非易失性存储器件包括：存储单元，包括电阻可变器件和用于控制流过电阻可变器件的电流的开关单元; 读取参考电压发生器，被配置为根据在所述开关单元中发生的偏斜产生参考电压; 以及感测放大器，被配置为基于所述参考电压来感测对应于流过所述电阻可变器件的电流的电压。
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公开(公告)号：US09123412B2
公开(公告)日：2015-09-01
申请号：US14018011
申请日：2013-09-04
CPC分类号： G11C13/003 , G11C11/1659 , G11C11/1673 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C2013/0054
摘要： According to one embodiment, a resistance change memory includes the following configuration. A first inverter includes first input and first output terminals and first and second voltage terminals. A second inverter includes second input and second output terminals and third and fourth voltage terminals. The second input terminal is connected to the first output terminal. The second output terminal is connected to the first input terminal. First and second transistors are connected to the first and second output terminals, respectively. Third and fourth transistors are connected to the first and third voltage terminals, respectively. A fifth transistor is connected between the first voltage terminal and the first memory cell. A sixth transistor is connected to the third voltage terminal. A controller turns on the first and second transistors, after turning off the fifth and sixth transistors.
摘要翻译： 根据一个实施例，电阻变化存储器包括以下配置。 第一反相器包括第一输入端和第一输出端以及第一和第二电压端。 第二反相器包括第二输入端和第二输出端以及第三和第四电压端。 第二输入端子连接到第一输出端子。 第二输出端子连接到第一输入端子。 第一和第二晶体管分别连接到第一和第二输出端子。 第三和第四晶体管分别连接到第一和第三电压端子。 第五晶体管连接在第一电压端和第一存储单元之间。 第六晶体管连接到第三电压端子。 在关闭第五和第六晶体管之后，控制器接通第一和第二晶体管。
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公开(公告)号：US20140286075A1
公开(公告)日：2014-09-25
申请号：US14018287
申请日：2013-09-04
申请人： Akira KATAYAMA , Masahiro TAKAHASHI , Tsuneo INABA , Hyuck Sang YIM , Dong Keun KIM , Byoung Chan OH , Ji Wang LEE
发明人： Akira KATAYAMA , Masahiro TAKAHASHI , Tsuneo INABA , Hyuck Sang YIM , Dong Keun KIM , Byoung Chan OH , Ji Wang LEE
CPC分类号： G11C13/004 , G11C5/06 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C2013/0054
摘要： According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.
摘要翻译： 根据一个实施例，存储器包括存储单元阵列，其包括沿列方向布置的块，第一和第二主全局导线，每列从列方向上从存储单元阵列的第一端延伸到第二端，第一电阻 连接在存储单元阵列内部的第一和第二主要全局导电线之间的改变元件，从列方向上从存储单元阵列的第一端延伸到第二端的第一参考全局导电线，以及连接到存储单元阵列的第二电阻变化元件 到存储单元阵列外的参考全局导线。
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公开(公告)号：US20140286080A1
公开(公告)日：2014-09-25
申请号：US14018011
申请日：2013-09-04
IPC分类号： G11C13/00
CPC分类号： G11C13/003 , G11C11/1659 , G11C11/1673 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C2013/0054
摘要： According to one embodiment, a resistance change memory includes the following configuration. A first inverter includes first input and first output terminals and first and second voltage terminals. A second inverter includes second input and second output terminals and third and fourth voltage terminals. The second input terminal is connected to the first output terminal. The second output terminal is connected to the first input terminal. First and second transistors are connected to the first and second output terminals, respectively. Third and fourth transistors are connected to the first and third voltage terminals, respectively. A fifth transistor is connected between the first voltage terminal and the first memory cell. A sixth transistor is connected to the third voltage terminal. A controller turns on the first and second transistors, after turning off the fifth and sixth transistors.
摘要翻译： 根据一个实施例，电阻变化存储器包括以下配置。 第一反相器包括第一输入端和第一输出端以及第一和第二电压端。 第二反相器包括第二输入端和第二输出端以及第三和第四电压端。 第二输入端子连接到第一输出端子。 第二输出端子连接到第一输入端子。 第一和第二晶体管分别连接到第一和第二输出端子。 第三和第四晶体管分别连接到第一和第三电压端子。 第五晶体管连接在第一电压端和第一存储单元之间。 第六晶体管连接到第三电压端子。 在关闭第五和第六晶体管之后，控制器接通第一和第二晶体管。
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