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公开(公告)号：US09123412B2
公开(公告)日：2015-09-01
申请号：US14018011
申请日：2013-09-04
CPC分类号： G11C13/003 , G11C11/1659 , G11C11/1673 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C2013/0054
摘要： According to one embodiment, a resistance change memory includes the following configuration. A first inverter includes first input and first output terminals and first and second voltage terminals. A second inverter includes second input and second output terminals and third and fourth voltage terminals. The second input terminal is connected to the first output terminal. The second output terminal is connected to the first input terminal. First and second transistors are connected to the first and second output terminals, respectively. Third and fourth transistors are connected to the first and third voltage terminals, respectively. A fifth transistor is connected between the first voltage terminal and the first memory cell. A sixth transistor is connected to the third voltage terminal. A controller turns on the first and second transistors, after turning off the fifth and sixth transistors.
摘要翻译： 根据一个实施例，电阻变化存储器包括以下配置。 第一反相器包括第一输入端和第一输出端以及第一和第二电压端。 第二反相器包括第二输入端和第二输出端以及第三和第四电压端。 第二输入端子连接到第一输出端子。 第二输出端子连接到第一输入端子。 第一和第二晶体管分别连接到第一和第二输出端子。 第三和第四晶体管分别连接到第一和第三电压端子。 第五晶体管连接在第一电压端和第一存储单元之间。 第六晶体管连接到第三电压端子。 在关闭第五和第六晶体管之后，控制器接通第一和第二晶体管。
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公开(公告)号：US09741434B2
公开(公告)日：2017-08-22
申请号：US14018287
申请日：2013-09-04
申请人： Akira Katayama , Masahiro Takahashi , Tsuneo Inaba , Hyuck Sang Yim , Dong Keun Kim , Byoung Chan Oh , Ji Wang Lee
发明人： Akira Katayama , Masahiro Takahashi , Tsuneo Inaba , Hyuck Sang Yim , Dong Keun Kim , Byoung Chan Oh , Ji Wang Lee
CPC分类号： G11C13/004 , G11C5/06 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C2013/0054
摘要： According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.
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公开(公告)号：US09336871B2
公开(公告)日：2016-05-10
申请号：US14811237
申请日：2015-07-28
CPC分类号： G11C13/003 , G11C11/1659 , G11C11/1673 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C2013/0054
摘要： According to one embodiment, a resistance change memory includes the following configuration. A first inverter includes first input and first output terminals and first and second voltage terminals. A second inverter includes second input and second output terminals and third and fourth voltage terminals. The second input terminal is connected to the first output terminal. The second output terminal is connected to the first input terminal. First and second transistors are connected to the first and second output terminals, respectively. Third and fourth transistors are connected to the first and third voltage terminals, respectively. A fifth transistor is connected between the first voltage terminal and the first memory cell. A sixth transistor is connected to the third voltage terminal. A controller turns on the first and second transistors, after turning off the fifth and sixth transistors.
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公开(公告)号：US09001559B2
公开(公告)日：2015-04-07
申请号：US14018242
申请日：2013-09-04
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C11/1673 , G11C11/1693 , G11C13/00 , G11C13/0026 , G11C13/0061 , G11C2013/0045 , G11C2013/0054 , G11C2213/79
摘要： According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.
摘要翻译： 根据一个实施例，电阻变化存储器包括存储单元，读出放大器和全局位线。 存储单元设置在局部位线和字线相交的位置。 存储单元连接到本地位线和字线。 读出放大器通过向存储单元提供读取电流来读取存储在存储单元上的数据。 全局位线连接在本地位线和读出放大器之间。 全局位线将由读出放大器提供的读取电流馈送到本地位线。 在本地位线和全局位线彼此连接之前，读出放大器对全局位线进行充电。
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5.发明授权Electronic device including memory arrays with variable resistance storage elements arranged on different sides of a word line driving unit 有权电子设备包括具有布置在字线驱动单元的不同侧上的可变电阻存储元件的存储器阵列公开(公告)号：US09535834B2
公开(公告)日：2017-01-03
申请号：US14563645
申请日：2014-12-08
申请人： Dong-Keun Kim , Masahiro Takahashi , Tsuneo Inaba
发明人： Dong-Keun Kim , Masahiro Takahashi , Tsuneo Inaba
IPC分类号： G06F12/08 , G11C13/00 , G11C11/4099 , G11C11/16
CPC分类号： G11C13/004 , G06F3/061 , G06F3/0656 , G06F3/0679 , G06F12/0207 , G06F12/08 , G06F12/0875 , G06F2212/2024 , G06F2212/452 , G06F2212/60 , G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/4099 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C2013/0054 , G11C2213/79 , G11C2213/82
摘要： An electronic device includes a semiconductor device, wherein the semiconductor device includes: a word line driving unit for driving a plurality of word lines; a first cell array arranged at one side of the word line driving unit; a second cell array arranged at the other side of the word line driving unit; a bias voltage generation unit, arranged between the first cell array and the second cell array, for generating a bias voltage based on currents flowing through the first reference resistance element included in the first cell array and the second reference resistance element included in the second cell array; a first read control unit; and a second read control unit.
摘要翻译： 电子设备包括半导体器件，其中半导体器件包括：用于驱动多个字线的字线驱动单元; 布置在字线驱动单元的一侧的第一单元阵列; 布置在所述字线驱动单元的另一侧的第二单元阵列; 布置在所述第一单元阵列和所述第二单元阵列之间的偏置电压产生单元，用于基于流过所述第一单元阵列中包括的所述第一参考电阻元件的电流和所述第二单元中包括的所述第二参考电阻元件来产生偏置电压 阵列 第一读取控制单元; 和第二读取控制单元。
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公开(公告)号：US09484091B2
公开(公告)日：2016-11-01
申请号：US14636740
申请日：2015-03-03
CPC分类号： G11C13/004 , G11C11/1673 , G11C11/1693 , G11C13/00 , G11C13/0026 , G11C13/0061 , G11C2013/0045 , G11C2013/0054 , G11C2213/79
摘要： According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.
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公开(公告)号：US08947920B2
公开(公告)日：2015-02-03
申请号：US14018148
申请日：2013-09-04
申请人： Masahiro Takahashi , Tsuneo Inaba , Dong Keun Kim , Ji Wang Lee
发明人： Masahiro Takahashi , Tsuneo Inaba , Dong Keun Kim , Ji Wang Lee
CPC分类号： G11C11/1673 , G11C11/161 , G11C11/1659
摘要： According to one embodiment, a memory device includes a memory cell, a sense amplifier, unit structures and a reference signal generator. Each structure includes a first end, a first transistor, a first local line, a variable resistance element, a second transistor, a second local line, and a third transistor coupled in series. The reference signal generator includes first to fourth global lines, and first and second ones of the unit structures. The first unit structure is coupled at the first end to the first global line and coupled at the second end to the third global line. The second unit structure is coupled at the first end to the fourth global line and coupled at the second end to the second global line.
摘要翻译： 根据一个实施例，存储器件包括存储器单元，读出放大器，单元结构和参考信号发生器。 每个结构包括第一端，第一晶体管，第一局部线，可变电阻元件，第二晶体管，第二本地线和串联耦合的第三晶体管。 参考信号发生器包括第一至第四全局线，以及第一和第二单元结构。 第一单元结构在第一端耦合到第一全局线并且在第二端耦合到第三全局线。 第二单元结构在第一端耦合到第四全局线并且在第二端耦合到第二全局线。
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公开(公告)号：US09263114B2
公开(公告)日：2016-02-16
申请号：US14563690
申请日：2014-12-08
申请人： Ji-Wang Lee , Dong-Keun Kim , Masahiro Takahashi , Tsuneo Inaba
发明人： Ji-Wang Lee , Dong-Keun Kim , Masahiro Takahashi , Tsuneo Inaba
CPC分类号： G11C11/1673 , G11C11/15 , G11C11/16 , G11C11/1659 , G11C11/5607 , G11C11/5657 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C16/28 , G11C2013/0054 , G11C2213/79
摘要： A semiconductor memory unit includes first to Nth variable resistance elements each having different resistance values according to values stored therein, wherein N is a natural number equal to or greater than 2; a reference resistance element having a first reference resistance value; and first to Nth comparison units which correspond to the first to Nth variable resistance elements, respectively, and each of which determines whether a resistance value of the corresponding variable resistance element is greater or less than a second reference resistance value, wherein the first to Nth comparison units are commonly coupled to the reference resistance element.
摘要翻译： 半导体存储单元包括根据存储在其中的值具有不同电阻值的第一至第N可变电阻元件，其中N是等于或大于2的自然数; 具有第一参考电阻值的参考电阻元件; 以及分别对应于第一至第N可变电阻元件的第一至第N比较单元，并且每个比较单元确定相应的可变电阻元件的电阻值是否大于或小于第二参考电阻值，其中第一至第N 比较单元通常耦合到参考电阻元件。
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公开(公告)号：US09177641B2
公开(公告)日：2015-11-03
申请号：US14018306
申请日：2013-09-04
申请人： Masahiro Takahashi , Tsuneo Inaba , Dong Keun Kim , Ji Wang Lee
发明人： Masahiro Takahashi , Tsuneo Inaba , Dong Keun Kim , Ji Wang Lee
CPC分类号： G11C13/004 , G11C11/1673 , G11C2013/0054 , G11C2213/79
摘要： According to one embodiment, a memory device includes a memory cell, a sense amplifier, and a resistor. The sense amplifier includes a first input and a second input, outputs a signal in accordance with a difference between the first and second inputs, and is selectively coupled at a second input to the memory cell. The resistor is in a first path between the first input of the sense amplifier and a ground node.
摘要翻译： 根据一个实施例，存储器件包括存储单元，读出放大器和电阻器。 读出放大器包括第一输入和第二输入，根据第一和第二输入之间的差输出信号，并且在第二输入端选择性地耦合到存储单元。 电阻器位于读出放大器的第一输入端和接地节点之间的第一路径中。
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公开(公告)号：US09911856B2
公开(公告)日：2018-03-06
申请号：US12900145
申请日：2010-10-07
IPC分类号： H01L29/786 , H01L29/423
CPC分类号： H01L29/7869 , H01L29/42384 , H01L29/78606 , H01L29/78696
摘要： One of objects is to provide a semiconductor device with stable electric characteristics, in which an oxide semiconductor is used. The semiconductor device includes a thin film transistor including an oxide semiconductor layer, and a silicon oxide layer over the thin film transistor. The thin film transistor includes a gate electrode layer, a gate insulating layer whose thickness is equal to or larger than 100 nm and equal to or smaller than 350 nm, the oxide semiconductor layer, a source electrode layer and a drain electrode layer. In the thin film transistor, the difference of the threshold voltage value is 1 V or less between before and after performance of a measurement in which the voltage of 30 V or −30 V is applied to the gate electrode layer at a temperature of 85° C. for 12 hours.
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