公开(公告)号：US20110284937A1

公开(公告)日：2011-11-24

申请号：US12858702

申请日：2010-08-18

Applicant: Hyung Jun KIM ,  Jin Dong Song ,  Hyun Cheol Koo ,  Kyung Ho Kim ,  Suk Hee Han

Inventor： Hyung Jun KIM ,  Jin Dong Song ,  Hyun Cheol Koo ,  Kyung Ho Kim ,  Suk Hee Han

IPC: H01L29/82

CPC classification number: H01L29/66984 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/18 ,  Y10S257/902

Abstract: A spin transistor that includes: a semiconductor substrate including an upper cladding layer and a lower cladding layer, and a channel layer interposed between the upper and lower cladding layers; a ferromagnetic source and a ferromagnetic drain formed on the semiconductor substrate and spaced from each other in a length direction of the channel layer; and a gate electrode formed on the semiconductor substrate between the source and the drain and having applied a gate voltage thereto to control a spin precession of an electron passing through the channel layer, wherein the semiconductor substrate includes a first carrier supply layer of a first conductivity type disposed below the lower cladding layer and supplying carriers to the channel layer, and a second carrier supply layer of a second conductivity type opposite to the first conductivity type formed on the upper cladding layer and supplying the carriers to the channel layer.

Abstract translation: 一种自旋晶体管，包括：包括上包层和下包层的半导体衬底，以及介于上包层和下包层之间的沟道层; 形成在所述半导体基板上并且在所述沟道层的长度方向上彼此间隔开的铁磁源和铁磁性漏极; 以及形成在所述源极和漏极之间的所述半导体衬底上并且施加了栅极电压以用于控制通过所述沟道层的电子的自旋进动的栅电极，其中所述半导体衬底包括具有第一导电性的第一载流子供应层 类型，其设置在所述下包层下方并且将沟道层供给到所述沟道层;以及第二导电类型的第二载流子供应层，其形成在所述上包层上并且将所述载流子提供给所述沟道层。

公开(公告)号：US20110279146A1

公开(公告)日：2011-11-17

申请号：US12899778

申请日：2010-10-07

Applicant: Hyun Cheol Koo ,  Suk Hee Han ,  Joon Yeon Chang ,  Hyung Jun Kim ,  Jun Woo Choi

Inventor： Hyun Cheol Koo ,  Suk Hee Han ,  Joon Yeon Chang ,  Hyung Jun Kim ,  Jun Woo Choi

IPC: H03K19/091

CPC classification number: H03K19/091 ,  B82Y10/00 ,  G11C11/16 ,  H03K19/18

Abstract: There is provided a complementary spin transistor logic circuit, including: a parallel spin transistor that includes a magnetized first source, a first drain magnetized in parallel with the magnetization direction of the first source, a first channel layer and a first gate electrode; and an anti-parallel spin transistor that includes a magnetized second source, a second drain magnetized in anti-parallel with the magnetization direction of the second source, a second channel layer and a second gate electrode, wherein the first gate electrode and the second gate electrode are connected to a common input terminal.

Abstract translation: 提供了一种互补自旋晶体管逻辑电路，包括：并联自旋晶体管，其包括磁化的第一源，与第一源的磁化方向平行磁化的第一漏极，第一沟道层和第一栅电极; 以及反并联自旋晶体管，其包括磁化的第二源极，与所述第二源极的磁化方向反并联的第二漏极，第二沟道层和第二栅电极，其中所述第一栅电极和所述第二栅极 电极连接到公共输入端子。

公开(公告)号：US07994555B2

公开(公告)日：2011-08-09

申请号：US11949659

申请日：2007-12-03

Applicant: Hyun-Cheol Koo ,  Suk-Hee Han ,  Joon-Yeon Chang ,  Hyung-Jun Kim ,  Jin-Seock Ma

Inventor： Hyun-Cheol Koo ,  Suk-Hee Han ,  Joon-Yeon Chang ,  Hyung-Jun Kim ,  Jin-Seock Ma

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: G11C11/16 ,  H01L29/20 ,  H01L29/66984

Abstract: A spin transistor useful for device miniaturization and high-density integration is provided. The spin transistor includes: a semiconductor substrate including a channel layer; ferromagnetic source and drain disposed on the semiconductor substrate to be separated from each other and to be magnetized in a direction perpendicular to a surface of the channel layer; a gate formed on the semiconductor substrate between the source and the drain to adjust spins of electrons passing through the channel layer, wherein spin-polarized electrons are injected from the source to the channel layer, and the electrons injected into the channel layer pass though the channel layer and are injected into the drain, and wherein the spins of the electrons passing through the channel layer undergo precession due to a spin-orbit coupling induced magnetic field according to a voltage of the gate.

Abstract translation: 提供了用于器件小型化和高密度集成的自旋晶体管。 自旋晶体管包括：包括沟道层的半导体衬底; 设置在半导体衬底上的铁磁源极和漏极彼此分离并沿垂直于沟道层表面的方向被磁化; 形成在源极和漏极之间的半导体衬底上的栅极，以调节通过沟道层的电子的旋转，其中自旋极化电子从源极注入沟道层，并且注入沟道层的电子通过 沟道层并且注入到漏极中，并且其中通过沟道层的电子的自旋由于根据栅极的电压的自旋 - 轨道耦合感应磁场而进行进动。

公开(公告)号：US20110042648A1

公开(公告)日：2011-02-24

申请号：US12684586

申请日：2010-01-08

Applicant: Hyun Cheol Koo ,  Suk Hee Han ,  Joon Yeon Chang ,  Hyung Jun Kim ,  Jang Hae Ku

Inventor： Hyun Cheol Koo ,  Suk Hee Han ,  Joon Yeon Chang ,  Hyung Jun Kim ,  Jang Hae Ku

IPC: H01L29/82 ,  H01L29/66

CPC classification number: H01L29/66984 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L29/0665 ,  H01L29/1606 ,  H01L29/7783

Abstract: A logic device includes: a substrate having a channel layer; two input terminal patterns of ferromagnetic material formed on the substrate and spaced apart from each other along a longitudinal direction of the channel layer so as to serve as the input terminals of a logic gate; and an output terminal pattern of ferromagnetic material formed on the substrate and disposed between the two input terminal patterns to serve as an output terminal of the logic gate. The output terminal pattern reads an output voltage by using spin accumulation and diffusion of electron spins which are injected into the channel layer from the input terminal patterns.

Abstract translation: 逻辑器件包括：具有沟道层的衬底; 铁磁材料的两个输入端子图案形成在基板上并且沿着沟道层的纵向方向彼此间隔开，以便用作逻辑门的输入端; 以及形成在所述基板上并且设置在所述两个输入端子图案之间以用作所述逻辑门的输出端子的铁磁材料的输出端子图案。 输出端子图案通过使用从输入端子图案注入到沟道层中的电子自旋的自旋累积和扩散来读取输出电压。

公开(公告)号：US07839675B2

公开(公告)日：2010-11-23

申请号：US12360964

申请日：2009-01-28

Applicant: Hyun Cheol Koo ,  Suk Hee Han ,  Joon Yeon Chang ,  Hyung Jun Kim

Inventor： Hyun Cheol Koo ,  Suk Hee Han ,  Joon Yeon Chang ,  Hyung Jun Kim

IPC: G11C11/18 ,  G11C11/00 ,  G11C11/14

CPC classification number: H01L43/065 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/18 ,  H01L27/226 ,  H01L29/66462 ,  H01L29/7781

Abstract: A magnetic memory device includes a substrate for reading and a magnetic memory cell. The substrate has a channel layer. The magnetic memory cell is formed on the substrate and has a magnetized magnetic material that transfers spin data to electrons passing the channel layer. Data stored in the magnetic memory cell are read by a voltage across both side ends of the channel layer that is generated when the electrons passing the channel layer deviate in the widthwise direction of the channel layer by a spin Hall effect.

Abstract translation: 磁存储器件包括用于读取的衬底和磁存储单元。 衬底具有通道层。 磁性存储单元形成在基板上，并具有将自旋数据传送到通过沟道层的电子的磁化磁性材料。 存储在磁存储单元中的数据被通过通道沟道层的电子通过沟道层的宽度方向偏离旋转霍尔效应而产生的沟道层的两侧端的电压读取。

公开(公告)号：US07608901B2

公开(公告)日：2009-10-27

申请号：US11777228

申请日：2007-07-12

Applicant: Hyun Cheol Koo ,  Jong Hwa Eom ,  Suk Hee Han ,  Joon Yeon Chang ,  Hyung Jun Kim

Inventor： Hyun Cheol Koo ,  Jong Hwa Eom ,  Suk Hee Han ,  Joon Yeon Chang ,  Hyung Jun Kim

IPC: H01L29/72

CPC classification number: H01L29/66984 ,  G11C11/16 ,  H01L29/0843 ,  Y10S257/902 ,  Y10S977/933

Abstract: Disclosed herein is a spin transistor including: a semiconductor substrate having a channel layer formed therein; first and second electrodes which are formed to be spaced apart from each other on the substrate at a predetermined distance along a longitudinal direction of the channel layer; a source and drain which include magnetized ferromagnetic materials and are formed to be spaced apart form each other between the first electrode and the second electrode at a predetermined distance along the longitudinal direction of the channel layer; and a gate which is formed on the substrate between the source and the drain, and adjusts spin orientations of electrons passing through the channel layer, wherein the electrons passing through the channel layer are spin-aligned at a lower side of the source by a stray magnetic field of the source and spin-filtered at a lower side of the drain by a stray field of the drain.

Abstract translation: 本文公开了一种自旋晶体管，包括：其中形成有沟道层的半导体衬底; 第一和第二电极，沿着沟道层的纵向以预定的距离形成在衬底上彼此间隔开; 源极和漏极，其包括磁化铁磁材料，并且沿着沟道层的纵向方向以预定的距离在第一电极和第二电极之间彼此间隔开形成间隔开的源极和漏极; 以及形成在源极和漏极之间的衬底上的栅极，并且调节通过沟道层的电子的自旋取向，其中通过沟道层的电子通过杂散在源的较低侧自旋对准 源极的磁场，并通过漏极的杂散场在漏极的下侧进行自旋滤波。

公开(公告)号：US08775139B2

公开(公告)日：2014-07-08

申请号：US13162406

申请日：2011-06-16

Applicant: Jae Wan Shim ,  Hyun Cheol Koo ,  Suk Hee Han ,  Byoung Chul Min ,  Jun Woo Choi ,  Kyung Ho Shin ,  Jin Dong Song

Inventor： Jae Wan Shim ,  Hyun Cheol Koo ,  Suk Hee Han ,  Byoung Chul Min ,  Jun Woo Choi ,  Kyung Ho Shin ,  Jin Dong Song

IPC: G06G7/50 ,  G06G7/48 ,  G06F17/50 ,  G06T13/20 ,  G06T13/80

CPC classification number: G06F17/5018 ,  G06F17/5009 ,  G06F2217/16 ,  G06T13/20 ,  G06T13/80

Abstract: A method for simulating fluid flow includes: discretizing a space in which a fluid flows into a regular lattice; assuming that fluid particles repetitively move and collide in the lattice; deriving a univariate polynomial equation by comparing the n-th (n is a non-negative integer) order momentum of velocity between the Maxwell-Boltzmann distribution and the discretized Maxwell-Boltzmann distribution; calculating the weight coefficients corresponding to the discrete velocities of the fluid particles based on the univariate polynomial equation; and deriving a lattice Boltzmann model using the weight coefficients. A lattice Boltzmann model with superior stability and accuracy may be derived easily.

Abstract translation: 用于模拟流体流动的方法包括：离散流体流入规则晶格的空间; 假设流体颗粒在格子中重复地移动和碰撞; 通过比较Maxwell-Boltzmann分布与离散Maxwell-Boltzmann分布之间的速度的第n（n是非负整数）阶次动量，得出单变量多项式方程; 基于单变量多项式方程计算与流体颗粒的离散速度对应的权重系数; 并使用权重系数导出格子波尔兹曼模型。 可以很容易地得出具有优异的稳定性和精度的晶格玻尔兹曼模型。

公开(公告)号：US08421060B2

公开(公告)日：2013-04-16

申请号：US12684586

申请日：2010-01-08

Applicant: Hyun Cheol Koo ,  Suk Hee Han ,  Joon Yeon Chang ,  Hyung Jun Kim ,  Jang Hae Ku

Inventor： Hyun Cheol Koo ,  Suk Hee Han ,  Joon Yeon Chang ,  Hyung Jun Kim ,  Jang Hae Ku

IPC: H01L29/82 ,  H01L29/66

CPC classification number: H01L29/66984 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L29/0665 ,  H01L29/1606 ,  H01L29/7783

Abstract: A logic device includes: a substrate having a channel layer; two input terminal patterns of ferromagnetic material formed on the substrate and spaced apart from each other along a longitudinal direction of the channel layer so as to serve as the input terminals of a logic gate; and an output terminal pattern of ferromagnetic material formed on the substrate and disposed between the two input terminal patterns to serve as an output terminal of the logic gate. The output terminal pattern reads an output voltage by using spin accumulation and diffusion of electron spins which are injected into the channel layer from the input terminal patterns.

Abstract translation: 逻辑器件包括：具有沟道层的衬底; 铁磁材料的两个输入端子图案形成在基板上并且沿着沟道层的纵向方向彼此间隔开，以便用作逻辑门的输入端; 以及形成在所述基板上并且设置在所述两个输入端子图案之间以用作所述逻辑门的输出端子的铁磁材料的输出端子图案。 输出端子图案通过使用从输入端子图案注入到沟道层中的电子自旋的自旋累积和扩散来读取输出电压。

公开(公告)号：US08183611B2

公开(公告)日：2012-05-22

申请号：US12858702

申请日：2010-08-18

Applicant: Hyung Jun Kim ,  Jin Dong Song ,  Hyun Cheol Koo ,  Kyung Ho Kim ,  Suk Hee Han

Inventor： Hyung Jun Kim ,  Jin Dong Song ,  Hyun Cheol Koo ,  Kyung Ho Kim ,  Suk Hee Han

IPC: H01L29/76

CPC classification number: H01L29/66984 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/18 ,  Y10S257/902

Abstract: A spin transistor that includes: a semiconductor substrate including an upper cladding layer and a lower cladding layer, and a channel layer interposed between the upper and lower cladding layers; a ferromagnetic source and a ferromagnetic drain formed on the semiconductor substrate and spaced from each other in a length direction of the channel layer; and a gate electrode formed on the semiconductor substrate between the source and the drain and having applied a gate voltage thereto to control a spin precession of an electron passing through the channel layer, wherein the semiconductor substrate includes a first carrier supply layer of a first conductivity type disposed below the lower cladding layer and supplying carriers to the channel layer, and a second carrier supply layer of a second conductivity type opposite to the first conductivity type formed on the upper cladding layer and supplying the carriers to the channel layer.

Abstract translation: 一种自旋晶体管，包括：包括上包层和下包层的半导体衬底，以及介于上包层和下包层之间的沟道层; 形成在所述半导体基板上并且在所述沟道层的长度方向上彼此间隔开的铁磁源和铁磁性漏极; 以及形成在所述源极和漏极之间的所述半导体衬底上并且施加了栅极电压以用于控制通过所述沟道层的电子的自旋进动的栅电极，其中所述半导体衬底包括具有第一导电性的第一载流子供应层 类型，其设置在所述下包层下方并且将沟道层供给到所述沟道层;以及第二导电类型的第二载流子供应层，其形成在所述上包层上并且将所述载流子提供给所述沟道层。

公开(公告)号：US20120007045A1

公开(公告)日：2012-01-12

申请号：US12911560

申请日：2010-10-25

Applicant: JIN-DONG SONG ,  Sang Hoon Shin ,  Hyung-jun Kim ,  Hyun Cheol Koo ,  Suk Hee Han ,  Joonyeon Chang

Inventor： JIN-DONG SONG ,  Sang Hoon Shin ,  Hyung-jun Kim ,  Hyun Cheol Koo ,  Suk Hee Han ,  Joonyeon Chang

IPC: H01L29/15 ,  H01L21/20

CPC classification number: H01L29/7783 ,  B82Y10/00 ,  H01L29/122

Abstract: Disclosed herein are a method of generating a two-dimensional hole gas (2DHG) using a type-2 quantum well formed using semiconductors with different electron affinities or band gap, and a high-speed p-type semiconductor device using the 2DHG. To this end, the method includes providing a semiconductor substrate; growing a first semiconductor layer on the semiconductor substrate, growing a second semiconductor layer with a different electron affinity or band gap from the first semiconductor layer on the first semiconductor layer, and growing a third semiconductor layer with a different electron affinity or band gap from the second semiconductor layer, thereby forming a type-2 quantum well; and forming a p-type doping layer in the vicinity of the type-2 quantum well, thereby generating the 2DHG.

Abstract translation: 本文公开了使用具有不同电子亲和性或带隙的半导体形成的2型量子阱和使用该2DHG的高速p型半导体器件来生成二维空穴气体（2DHG）的方法。 为此，该方法包括提供半导体衬底; 在所述半导体衬底上生长第一半导体层，在所述第一半导体层上生长具有与所述第一半导体层不同的电子亲和性或带隙的第二半导体层，以及生长具有与所述第一半导体层不同的电子亲和性或带隙的第三半导体层 第二半导体层，从而形成2型量子阱; 并在2型量子阱附近形成p型掺杂层，从而生成2DHG。