公开(公告)号：US12154979B2

公开(公告)日：2024-11-26

申请号：US17496186

申请日：2021-10-07

Applicant: IMEC VZW

Inventor： Aryan Afzalian

IPC: H01L29/772 ,  H03K17/687

Abstract: A field-effect transistor and a method for controlling such is provided herein. The field-effect transistor includes a source terminal and a drain terminal arranged on a first side of a semiconductor layer and a single gate arranged on a second side of the semiconductor layer opposite the first side. The gate and the source terminal are arranged to overlap with a first common region of the semiconductor layer and the gate and the drain terminal are arranged to overlap with a second common region of the semiconductor layer.

公开(公告)号：US20240213321A1

公开(公告)日：2024-06-27

申请号：US18545730

申请日：2023-12-19

Applicant: IMEC VZW

Inventor： Aryan Afzalian

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/43

CPC classification number: H01L29/0895 ,  H01L29/0665 ,  H01L29/1033 ,  H01L29/1606 ,  H01L29/432

Abstract: Example embodiments relate to tunneling enabled feedback field effect transistors (FETs). One example system includes a feedback field effect transistor. The feedback field effect transistor includes a source region. The feedback field effect transistor also includes a channel region. Additionally, the feedback field effect transistor includes a drain region. Further, the feedback field effect transistor includes a gate. The channel region is between the source region and the drain region. The source region, the channel region, and the drain region include a semiconductor material with a bandgap that is smaller than 0.9 eV. The source region or the drain region has a dopant concentration that is smaller than 5×1019 cm−3. The gate is positioned along the channel and isolated from the channel.

公开(公告)号：US20230178640A1

公开(公告)日：2023-06-08

申请号：US18060954

申请日：2022-12-01

Applicant: IMEC VZW

Inventor： Aryan Afzalian ,  Julien Ryckaert ,  Naoto Horiguchi

IPC: H01L29/775 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439

Abstract: A FET device (100) is provided, the FET device including a substrate (102), a source body (120), a drain body (130) and a set of vertically spaced apart channel layers (150) extending between the source and drain body in a first direction along the substrate (102), the source body (120) comprising a common source body portion (122) arranged at a first lateral side of the set of channel layers (150) and a set of vertically spaced apart source prongs (124) protruding from the common source body portion (122) in a second direction along the substrate (102), transverse to the first direction, the drain body (130) comprising a common source body portion (132) arranged at the first lateral side of the set of channel layers (150) and a set of drain prongs (134) protruding from the common drain body portion (132) in the second direction; and a gate body (140) comprising a common gate body portion (142) arranged at a second lateral side of the channel layer (150), opposite the first lateral side, and a set of gate prongs (144) protruding from the common gate body gate portion (142) in a third direction along the substrate (102), opposite the first direction; wherein each channel layer (150) comprises a first side (150aa, 150ba) and an opposite second side (150ab, 150bb), the first side arranged in abutment with a topside or an underside of a pair of source and drain prongs (124a, 134a) and the second side (150ab, 150bb) facing a gate prong (144a, 144b).

公开(公告)号：US20230178635A1

公开(公告)日：2023-06-08

申请号：US18074294

申请日：2022-12-02

Applicant: IMEC VZW

Inventor： Aryan Afzalian ,  Julien Ryckaert ,  Naoto Horiguchi ,  Boon Teik Chan

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L21/308 ,  H01L21/322 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L29/785 ,  H01L29/0847 ,  H01L29/1033 ,  H01L21/308 ,  H01L21/322 ,  H01L21/0262

Abstract: A method for forming a FET device is provided, the method including: forming a fin structure; while masking the fin structure from a second side of the fin structure opposite a first side of the fin structure: etching each of first and second fin parts laterally from the first side such that a set of source cavities and a set of drain cavities is formed in first non-channel layers in the first fin part and the second fin part, and subsequently, forming a source body and a drain body, each comprising a respective common body portion along the first side and a set of prongs protruding from the respective common body portion into the source and drain cavities, respectively, and abutting the channel layers; and while masking the fin structure from the first side: etching the third fin part laterally from the second side such that a set of gate cavities extending through the third fin part is formed in second non-channel layers, and subsequently, forming a gate body comprising a common gate body portion along the second side and a set of gate prongs protruding from the common gate body portion into the gate cavities.