公开(公告)号：US08630181B2

公开(公告)日：2014-01-14

申请号：US13463640

申请日：2012-05-03

申请人： Daniele Mangano ,  Giuseppe Falconeri ,  Ignazio Antonino Urzi′

发明人： Daniele Mangano ,  Giuseppe Falconeri ,  Ignazio Antonino Urzi′

IPC分类号： H04L1/00 ,  H04L12/28 ,  G06F15/173

CPC分类号： H04L47/26 ,  H04L47/2441

摘要： A communication system transmits data from a first circuit over a communication channel to a second circuit, the data having a first priority and a second priority. The communication system includes a separation circuit, a first-in first-out (FIFO) memory, and a control circuit.

摘要翻译： 通信系统通过通信信道将数据从第一电路发送到第二电路，该数据具有第一优先级和第二优先级。 通信系统包括分离电路，先进先出（FIFO）存储器和控制电路。

公开(公告)号：US20120281713A1

公开(公告)日：2012-11-08

申请号：US13463640

申请日：2012-05-03

申请人： Daniele MANGANO ,  Giuseppe Falconeri ,  Ignazio Antonino Urzi'

发明人： Daniele MANGANO ,  Giuseppe Falconeri ,  Ignazio Antonino Urzi'

IPC分类号： H04L12/413

CPC分类号： H04L47/26 ,  H04L47/2441

摘要： A communication system transmits data from a first circuit over a communication channel to a second circuit, the data having a first priority and a second priority. The communication system includes a separation circuit, a first-in first-out (FIFO) memory, and a control circuit.

摘要翻译： 通信系统通过通信信道将数据从第一电路传送到第二电路，该数据具有第一优先级和第二优先级。 通信系统包括分离电路，先进先出（FIFO）存储器和控制电路。

公开(公告)号：US20120210093A1

公开(公告)日：2012-08-16

申请号：US13028383

申请日：2011-02-16

申请人： Ignazio Antonino URZI ,  Philippe D'AUDIGIER ,  Olivier SAUVAGE ,  Stuart RYAN ,  Andrew Michael JONES

发明人： Ignazio Antonino URZI ,  Philippe D'AUDIGIER ,  Olivier SAUVAGE ,  Stuart RYAN ,  Andrew Michael JONES

IPC分类号： G06F12/02

CPC分类号： G06F13/385 ,  A01C7/04 ,  A01C7/20 ,  G06F15/173 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/014

摘要： A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to receive the transaction request including at least first source identity information, wherein the first source identity information is associated with a source of the transaction request on the further die. The mapping circuitry is configured to modify the transaction request to replace the first source identity information with local source identity information, wherein that local source identity information is associated with the mapping circuitry. The mapping circuitry is configured to modify the received transaction request to provide said first source identity information in a further field.

摘要翻译： 包装包括模具和至少一个另外的模具。 管芯具有被配置为经由互连从另外的管芯接收事务请求并且经由互连将对事务请求的响应发送到所述另外管芯的接口。 芯片还具有映射电路，其被配置为接收包括至少第一源标识信息的事务请求，其中第一源标识信息与另外裸片上的事务请求的源相关联。 映射电路被配置为修改事务请求以用本地源标识信息替换第一源标识信息，其中本地源标识信息与映射电路相关联。 映射电路被配置为修改所接收的事务请求以在另外的字段中提供所述第一源标识信息。

公开(公告)号：US20120159095A1

公开(公告)日：2012-06-21

申请号：US13324838

申请日：2011-12-13

申请人： Daniele Mangano ,  Salvatore Pisasale ,  Ignazio Antonino Urzi'

发明人： Daniele Mangano ,  Salvatore Pisasale ,  Ignazio Antonino Urzi'

IPC分类号： G06F12/00

CPC分类号： G06F13/4059 ,  G06F1/12 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/42

摘要： An interface system for interfacing an asynchronous circuit with a synchronous circuit, wherein the synchronous circuit samples, in response to a clock signal, a first data signal when a first control signal indicates that the first data signal contains valid data, and wherein the asynchronous circuit generates a second data signal according to an asynchronous communication protocol. The system includes a FIFO memory, a control circuit for asynchronously writing the second data signal in the memory when the second data signal indicates the start of a communication, and synchronously reading the second data signal from the memory in response to a clock signal, and a conversion circuit for decoding, according to a asynchronous communication protocol, the second data signal read from the memory in a decoded data signal, wherein the decoded data signal corresponds to the first data signal.

摘要翻译： 一种用于将异步电路与同步电路接口的接口系统，其中当第一控制信号指示第一数据信号包含有效数据时，同步电路响应于时钟信号采样第一数据信号，并且其中异步电路 根据异步通信协议生成第二数据信号。 该系统包括FIFO存储器，当第二数据信号指示通信开始时，用于将第二数据信号异步写入存储器中的控制电路，以及响应于时钟信号从存储器同步读取第二数据信号，以及 一种转换电路，用于根据异步通信协议在解码的数据信号中解码从存储器读取的第二数据信号，其中解码的数据信号对应于第一数据信号。

公开(公告)号：US20120159017A1

公开(公告)日：2012-06-21

申请号：US13326991

申请日：2011-12-15

申请人： Ignazio Antonino URZI ,  Philippe D'AUDIGIER ,  Daniele MANGANO

发明人： Ignazio Antonino URZI ,  Philippe D'AUDIGIER ,  Daniele MANGANO

IPC分类号： G06F13/14

CPC分类号： G06F15/7842 ,  G06F15/7825

摘要： A node having a node input is configured to receive a plurality of transactions intended for a plurality of different targets. The node has multiple node outputs. At least one target is provided, that target including an input configured to receive a respective output of the node. The node is configured to direct transactions to the at least one target or an output (for passing to a different partition) depending on whether the transactions are intended for the target or a different target. This determination is made in response to a conversion operation which converts a target address of the transaction to an identification associated with the target or the output.

摘要翻译： 具有节点输入的节点被配置为接收用于多个不同目标的多个事务。 该节点具有多个节点输出。 提供至少一个目标，该目标包括被配置为接收节点的相应输出的输入。 该节点被配置为根据事务是针对目标还是不同的目标将事务定向到至少一个目标或输出（用于传递到不同的分区）。 响应于将交易的目标地址转换为与目标或输出相关联的标识的转换操作进行该确定。

公开(公告)号：US20120079148A1

公开(公告)日：2012-03-29

申请号：US13248316

申请日：2011-09-29

申请人： Ignazio Antonino URZI ,  Daniele MANGANO

发明人： Ignazio Antonino URZI ,  Daniele MANGANO

IPC分类号： G06F13/00

CPC分类号： G06F13/1626

摘要： An embodiment of a network-on-chip is provided. The network-on-chip includes a plurality of sources of requests and a plurality of destinations for requests. The plurality of destinations are configured to provide respective responses to respective requests. The network-on-chip further includes an interconnect for routing said requests and respective responses to said requests to and from the plurality of sources and at least one transaction reordering arrangement. The transaction reordering arrangement is configured to reorder said responses such that said responses are provided to a respective source in an order which corresponds to an order in which the requests are issued by said respective source. A respective transaction reordering arrangement is associated with a respective source.

摘要翻译： 提供了片上网络的实施例。 片上网络包括多个请求源和用于请求的多个目的地。 多个目的地被配置为向相应的请求提供相应的响应。 片上网络还包括用于将所述请求和对来自多个源的所述请求的各个响应以及至少一个事务重新排序装置进行路由的互连。 交易重排布置被配置为重新排序所述响应，使得所述响应以对应于由所述相应源发出请求的顺序的顺序提供给相应的源。 相应的事务重新排列布置与相应的源相关联。

公开(公告)号：US08782302B2

公开(公告)日：2014-07-15

申请号：US13326991

申请日：2011-12-15

申请人： Ignazio Antonino Urzi ,  Philippe D'Audigier ,  Daniele Mangano

发明人： Ignazio Antonino Urzi ,  Philippe D'Audigier ,  Daniele Mangano

IPC分类号： G06F3/00 ,  G06F5/00 ,  G06F13/00

CPC分类号： G06F15/7842 ,  G06F15/7825

摘要： A node having a node input is configured to receive a plurality of transactions intended for a plurality of different targets. The node has multiple node outputs. At least one target is provided, that target including an input configured to receive a respective output of the node. The node is configured to direct transactions to the at least one target or an output (for passing to a different partition) depending on whether the transactions are intended for the target or a different target. This determination is made in response to a conversion operation which converts a target address of the transaction to an identification associated with the target or the output.

摘要翻译： 具有节点输入的节点被配置为接收用于多个不同目标的多个事务。 该节点具有多个节点输出。 提供至少一个目标，该目标包括被配置为接收节点的相应输出的输入。 该节点被配置为根据事务是针对目标还是不同的目标将事务定向到至少一个目标或输出（用于传递到不同的分区）。 响应于将交易的目标地址转换为与目标或输出相关联的标识的转换操作进行该确定。

公开(公告)号：US08780935B2

公开(公告)日：2014-07-15

申请号：US13327419

申请日：2011-12-15

申请人： Daniele Mangano ,  Ignazio Antonino Urzi′

发明人： Daniele Mangano ,  Ignazio Antonino Urzi′

IPC分类号： H04J3/16

CPC分类号： G06F13/4059

摘要： A communication system includes interfacing between a first synchronous circuit and a second synchronous circuit. The system includes a first interface system and a second interface system. The first interface system receives data from the first synchronous circuit, and encodes the data according to an asynchronous communication protocol. The encoded data are transmitted over a communication channel to the second interface system. The second interface system decodes the data and transmits the decoded data to the second synchronous circuit. The first interface system includes a first FIFO memory for storing temporarily the data received from the first synchronous circuit and the second interface system includes a second FIFO memory for storing temporarily the data transmitted over the communication channel.

摘要翻译： 通信系统包括第一同步电路和第二同步电路之间的接口。 该系统包括第一接口系统和第二接口系统。 第一接口系统从第一同步电路接收数据，并根据异步通信协议对数据进行编码。 编码数据通过通信信道发送到第二接口系统。 第二接口系统解码数据并将解码的数据发送到第二同步电路。 第一接口系统包括用于临时存储从第一同步电路接收的数据的第一FIFO存储器，第二接口系统包括用于临时存储在通信信道上发送的数据的第二FIFO存储器。

公开(公告)号：US08521937B2

公开(公告)日：2013-08-27

申请号：US13028383

申请日：2011-02-16

申请人： Ignazio Antonino Urzi ,  Philippe D'Audigier ,  Olivier Sauvage ,  Stuart Ryan ,  Andrew Michael Jones

发明人： Ignazio Antonino Urzi ,  Philippe D'Audigier ,  Olivier Sauvage ,  Stuart Ryan ,  Andrew Michael Jones

IPC分类号： G06F13/14 ,  G06F13/38

CPC分类号： G06F13/385 ,  A01C7/04 ,  A01C7/20 ,  G06F15/173 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/014

摘要： A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to receive the transaction request including at least first source identity information, wherein the first source identity information is associated with a source of the transaction request on the further die. The mapping circuitry is configured to modify the transaction request to replace the first source identity information with local source identity information, wherein that local source identity information is associated with the mapping circuitry. The mapping circuitry is configured to modify the received transaction request to provide said first source identity information in a further field.

摘要翻译： 包装包括模具和至少一个另外的模具。 管芯具有被配置为经由互连从另外的管芯接收事务请求并且经由互连将对事务请求的响应发送到所述另外管芯的接口。 芯片还具有映射电路，其被配置为接收包括至少第一源标识信息的事务请求，其中第一源标识信息与另外裸片上的事务请求的源相关联。 映射电路被配置为修改事务请求以用本地源标识信息替换第一源标识信息，其中本地源标识信息与映射电路相关联。 映射电路被配置为修改所接收的事务请求以在另外的字段中提供所述第一源标识信息。

公开(公告)号：US20130061016A1

公开(公告)日：2013-03-07

申请号：US13605880

申请日：2012-09-06

申请人： Ignazio Antonino Urzi ,  Nicolas Graciannette

发明人： Ignazio Antonino Urzi ,  Nicolas Graciannette

IPC分类号： G06F12/00 ,  G06F12/14

CPC分类号： G06F21/79

摘要： A first engine and a memory access controller are each configured to receive memory operation information in parallel. In response to receiving the memory operation information, the first engine is prepared to perform a function on memory data associated with the memory operation and the memory controller is configured to prepare the memory to cause the memory operation to be performed.

摘要翻译： 第一引擎和存储器访问控制器各自被配置为并行地接收存储器操作信息。 响应于接收到存储器操作信息，第一引擎准备执行与存储器操作相关联的存储器数据的功能，并且存储器控制器被配置为准备存储器以使得执行存储器操作。