公开(公告)号：US08168521B2

公开(公告)日：2012-05-01

申请号：US12725743

申请日：2010-03-17

Applicant: In-Sang Jeon ,  Si-Hyung Lee ,  Jong-Ryeol Yoo ,  Yu-Ghun Shin ,  Suk-Hun Choi

Inventor： In-Sang Jeon ,  Si-Hyung Lee ,  Jong-Ryeol Yoo ,  Yu-Ghun Shin ,  Suk-Hun Choi

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/4236 ,  H01L21/67207 ,  H01L21/823437 ,  H01L21/823456 ,  H01L29/66621 ,  H01L29/78

Abstract: In a method of manufacturing a semiconductor device, a recess is formed in an active region of a substrate. A gate insulation layer is formed in the first recess. A barrier layer is formed on the gate insulation layer. A preliminary nucleation layer having a first resistance is formed on the barrier layer. The preliminary nucleation layer is converted into a nucleation layer having a second resistance substantially smaller than the first resistance. A conductive layer is formed on the nucleation layer. The conductive layer, the nucleation layer, the barrier layer and the gate insulation layer are partially etched to form a buried gate structure including a gate insulation layer pattern, a barrier layer pattern, a nucleation layer pattern and a conductive layer pattern.

Abstract translation: 在制造半导体器件的方法中，在衬底的有源区中形成凹部。 在第一凹部中形成栅极绝缘层。 在栅绝缘层上形成阻挡层。 在阻挡层上形成具有第一电阻的预成核层。 将初始成核层转变成具有比第一电阻显着小的第二电阻的成核层。 在成核层上形成导电层。 部分蚀刻导电层，成核层，势垒层和栅极绝缘层，以形成包括栅极绝缘层图案，势垒层图案，成核层图案和导电层图案的掩埋栅极结构。

公开(公告)号：US20080164508A1

公开(公告)日：2008-07-10

申请号：US11655689

申请日：2007-01-19

Applicant: In-Sang Jeon ,  Sang-Bom Kang ,  Dong-Chan Kim ,  Chul-Sung Kim ,  Sug-Hun Hong ,  Sang-Jin Hyun

Inventor： In-Sang Jeon ,  Sang-Bom Kang ,  Dong-Chan Kim ,  Chul-Sung Kim ,  Sug-Hun Hong ,  Sang-Jin Hyun

IPC: H01L29/788

CPC classification number: H01L21/28282 ,  H01L29/513 ,  H01L29/792 ,  Y10S257/908

Abstract: The memory device includes a first tunnel insulation layer pattern on a semiconductor substrate, a second tunnel insulation layer pattern having an energy band gap lower than that of the first tunnel insulation layer pattern on the first tunnel insulation layer pattern, a charge trapping layer pattern on the second tunnel insulation layer pattern, a blocking layer pattern on the charge trapping layer pattern, and a gate electrode on the blocking layer pattern. The memory device further includes a source/drain region at an upper portion of the semiconductor substrate, The upper portion of the semiconductor substrate is adjacent to the first tunnel insulation layer pattern.

Abstract translation: 存储器件包括在半导体衬底上的第一隧道绝缘层图案，第二隧道绝缘层图案，其第一隧道绝缘层图案上具有比第一隧道绝缘层图案低的能带隙， 第二隧道绝缘层图案，电荷俘获层图案上的阻挡层图案，以及阻挡层图案上的栅电极。 存储器件还包括在半导体衬底的上部的源极/漏极区域。半导体衬底的上部与第一隧道绝缘层图案相邻。

公开(公告)号：US06458701B1

公开(公告)日：2002-10-01

申请号：US09686622

申请日：2000-10-12

Applicant: Yun-sook Chae ,  Sang-bom Kang ,  Gil-heyun Choi ,  In-sang Jeon

Inventor： Yun-sook Chae ,  Sang-bom Kang ,  Gil-heyun Choi ,  In-sang Jeon

IPC: C23L1608

CPC classification number: C23C16/0281 ,  C23C16/0218 ,  C23C16/14 ,  H01L21/28556 ,  H01L21/28568

Abstract: A method for forming a metal layer located over a metal underlayer of a semiconductor device, using a metal halogen gas. The method involves supplying a predetermined reaction gas into a reaction chamber for a predetermined period of time prior to deposition of the metal layer. The reaction gas has a higher reactivity with an active halogen element of a metal halogen gas supplied to form the metal layer, compared to a metal element of the metal halogen gas. As the metal halogen gas is supplied into the reaction chamber, the reaction gas reacts with the halogen radicals of the metal halogen gas, so that the metal underlayer is protected from being contaminated by impurities containing the halogen radicals.

Abstract translation: 一种使用金属卤素气体形成位于半导体器件的金属底层上的金属层的方法。 该方法包括在沉积金属层之前将预定的反应气体提供给反应室预定的时间。 与金属卤素气体的金属元素相比，反应气体与供给的金属卤素气体的活性卤素元素的反应性较高，形成金属层。 当将金属卤素气体供应到反应室中时，反应气体与金属卤素气体的卤素自由基反应，从而保护金属底层免受含有卤素基团的杂质的污染。

公开(公告)号：US06348376B2

公开(公告)日：2002-02-19

申请号：US09765531

申请日：2001-01-19

Applicant: Hyun-Seok Lim ,  Sang-Bom Kang ,  In-Sang Jeon ,  Gil-Heyun Choi

Inventor： Hyun-Seok Lim ,  Sang-Bom Kang ,  In-Sang Jeon ,  Gil-Heyun Choi

IPC: H01L218242

CPC classification number: H01L21/76843 ,  C23C16/34 ,  C23C16/45553 ,  H01L21/28562 ,  H01L21/76804 ,  H01L28/91

Abstract: A method of forming a metal nitride film using chemical vapor deposition (CVD), and a method of forming a metal contact and a semiconductor capacitor of a semiconductor device using the same, are provided. The method of forming a metal nitride film using chemical vapor deposition (CVD) in which a metal source and a nitrogen source are used as a precursor, includes the steps of inserting a semiconductor substrate into a deposition chamber, flowing the metal source into the deposition chamber, removing the metal source remaining in the deposition chamber by cutting off the inflow of the metal source and flowing a purge gas into the deposition chamber, cutting off the purge gas and flowing the nitrogen source into the deposition chamber to react with the metal source adsorbed on the semiconductor substrate, and removing the nitrogen source remaining in the deposition chamber by cutting off the inflow of the nitrogen source and flowing the purge gas into the deposition chamber. Accordingly, the metal nitride film having low resistivity and a low content of Cl even with excellent step coverage can be formed at a temperature of 500° C. or lower, and a semiconductor capacitor having excellent leakage current characteristics can be manufactured. Also, a deposition speed, approximately 20 A/cycle, is suitable for mass production.

Abstract translation: 提供了使用化学气相沉积（CVD）形成金属氮化物膜的方法，以及使用其形成半导体器件的金属接触和半导体电容器的方法。 使用其中使用金属源和氮源作为前体的化学气相沉积（CVD）形成金属氮化物膜的方法包括以下步骤：将半导体衬底插入淀积室中，使金属源流入沉积物 通过切断金属源的流入并将净化气体流入沉积室，去除沉积室中残留的金属源，切断净化气体并使氮源流入沉积室以与金属源反应 吸附在半导体衬底上，并且通过切断氮源的流入并将净化气体流入沉积室来除去留在沉积室中的氮源。 因此，可以在500℃以下的温度下形成具有低电阻率和低Cl含量的金属氮化物膜，并且可以制造具有优异的漏电流特性的半导体电容器。 此外，大约20A /周的沉积速度适合于批量生产。

公开(公告)号：US08748254B2

公开(公告)日：2014-06-10

申请号：US13494328

申请日：2012-06-12

Applicant: Kwang-wook Lee ,  Sang-jun Lee ,  In-seak Hwang ,  In-sang Jeon ,  Byoung-yong Gwak ,  Ho-kyun An

Inventor： Kwang-wook Lee ,  Sang-jun Lee ,  In-seak Hwang ,  In-sang Jeon ,  Byoung-yong Gwak ,  Ho-kyun An

IPC: H01L21/00

CPC classification number: H01L27/10852 ,  H01L21/76816 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L28/91

Abstract: A method of manufacturing a semiconductor device includes forming a bit line on a substrate comprising an active region; forming an interlayer insulating layer covering the bit line on the substrate; forming a first hole at a location of the active region through the interlayer insulating layer; forming a dummy contact layer by filling the first hole; forming a mold layer on the interlayer insulating layer and the dummy contact layer; forming a second hole at a location of the dummy contact layer through the mold layer; removing the dummy contact layer in the first hole through the second hole; forming an epitaxial layer on a portion of the active region, which is exposed at a lower surface of the first hole; and forming a lower electrode on internal surfaces of the first hole and the second hole.

Abstract translation: 制造半导体器件的方法包括在包括有源区的衬底上形成位线; 形成覆盖所述基板上的所述位线的层间绝缘层; 在有源区的位置通过层间绝缘层形成第一孔; 通过填充第一孔形成虚拟接触层; 在层间绝缘层和虚拟接触层上形成模层; 在所述模拟接触层的位置处通过所述模制层形成第二孔; 通过第二孔去除第一孔中的虚拟接触层; 在所述有源区的在所述第一孔的下表面处露出的部分上形成外延层; 以及在所述第一孔和所述第二孔的内表面上形成下电极。

公开(公告)号：US20100213541A1

公开(公告)日：2010-08-26

申请号：US12699650

申请日：2010-02-03

Applicant: In-sang Jeon ,  Si-hyung Lee ,  Jong-ryeol Yoo ,  Yu-gyun Shin ,  Suk-hun Choi

Inventor： In-sang Jeon ,  Si-hyung Lee ,  Jong-ryeol Yoo ,  Yu-gyun Shin ,  Suk-hun Choi

IPC: H01L29/78

CPC classification number: H01L29/4236 ,  H01L21/28088 ,  H01L21/28202 ,  H01L27/10876 ,  H01L27/11 ,  H01L27/11517 ,  H01L29/4966 ,  H01L29/518

Abstract: An integrated circuit device includes a semiconductor substrate including an active region defined by an isolation region and having at least one trench therein, a gate insulating layer formed in the at least one trench, a gate electrode layer having a nano-crystalline structure disposed on the gate insulating layer and a word line on the gate electrode layer in the at least one trench. The device may further include a capping layer on the word line.

Abstract translation: 一种集成电路器件包括：半导体衬底，包括由隔离区限定的有源区，其中至少有一个沟槽;在该至少一个沟槽中形成的栅极绝缘层，具有纳米晶体结构的栅电极层， 栅极绝缘层和在至少一个沟槽中的栅极电极层上的字线。 该装置还可以包括字线上的覆盖层。

公开(公告)号：US06478872B1

公开(公告)日：2002-11-12

申请号：US09467313

申请日：1999-12-20

Applicant: Yun-sook Chae ,  In-sang Jeon ,  Sang-bom Kang ,  Sang-in Lee ,  Kyu-wan Ryu

Inventor： Yun-sook Chae ,  In-sang Jeon ,  Sang-bom Kang ,  Sang-in Lee ,  Kyu-wan Ryu

IPC: C30B2500

CPC classification number: C30B25/14 ,  C23C16/45548 ,  C23C16/45565 ,  C23C16/45574

Abstract: A method of delivering two or more mutually-reactive reaction gases when a predetermined film is deposited on a substrate, and a shower head used in the gas delivery method, function to increase the film deposition rate while preventing formation of contaminating particles. In this method, one reaction gas is delivered toward the edge of the substrate, and the other reaction gases are delivered toward the central portion of the substrate, each of the reaction gases being delivered via an independent gas outlet to prevent the reaction gases from being mixed. In the shower head, separate passages are provided to prevent the first reaction gas from mixing with the other reaction gases by delivering the first reaction gas from outlets formed around the edge of the bottom surface of the shower head. The other reaction gases are delivered from outlets formed in the central portion of the bottom surface of the shower head. Accordingly, one of the mutually-reactive gases is delivered toward the central portion of the substrate, and the others are delivered toward the edge of the substrate.

Abstract translation: 当将预定的膜沉积在基底上时输送两个或更多个相互反应的反应气体的方法和用于气体输送方法的淋浴头的作用是提高膜沉积速率同时防止污染颗粒的形成。 在该方法中，一个反应气体被输送到基板的边缘，并且其它反应气体被输送到基板的中心部分，每个反应气体经由独立的气体出口输送，以防止反应气体 混合 在喷淋头中，设置分开的通道，以防止第一反应气体与其它反应气体混合，通过从喷淋头底表面的边缘周围形成的出口输送第一反应气体。 其他反应气体从形成在淋浴喷头的底面的中心部分的出口输送。 因此，相互反应的气体中的一种被输送到基板的中心部分，而其它的被传送到基板的边缘。

公开(公告)号：US06399491B2

公开(公告)日：2002-06-04

申请号：US09826946

申请日：2001-04-06

Applicant: In-sang Jeon ,  Sang-bom Kang ,  Hyun-seok Lim ,  Gil-heyun Choi

Inventor： In-sang Jeon ,  Sang-bom Kang ,  Hyun-seok Lim ,  Gil-heyun Choi

IPC: H01L2144

CPC classification number: C23C16/45531 ,  C23C16/45527 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/7685

Abstract: A method of manufacturing a barrier metal layer uses atomic layer deposition (ALD) as the mechanism for depositing the barrier metal. The method includes supplying a first source gas onto the entire surface of a semiconductor substrate in the form of a pulse, and supplying a second source gas, which reacts with the first source gas, onto the entire surface of the semiconductor substrate in the form of a pulse. In a first embodiment, the pulses overlap in time so that the second source gas reacts with part of the first source gas physically adsorbed at the surface of the semiconductor substrate to thereby form part of the barrier metal layer by chemical vapor deposition whereas another part of the second source gas reacts with the first source gas chemically adsorbed at the surface of the semiconductor substrate to thereby form part of the barrier metal layer by atomic layer deposition. Thus, the deposition rate is greater than if the barrier metal layer were only formed by ALD. In the second embodiment, an impurity-removing gas is used to remove impurities in the barrier metal layer. Thus, even if the gas supply scheme is set up to only use ALD in creating the barrier metal layer, the deposition rate can be increased without the usual accompanying increase in the impurity content of the barrier metal layer.

Abstract translation: 制造阻挡金属层的方法使用原子层沉积（ALD）作为沉积阻挡金属的机理。 该方法包括以脉冲的形式将第一源气体提供到半导体衬底的整个表面上，并将与第一源气体反应的第二源气体以 一脉 在第一实施例中，脉冲在时间上重叠，使得第二源气体与物理吸附在半导体衬底的表面处的第一源气体的一部分反应，从而通过化学气相沉积形成阻挡金属层的一部分，而另一部分 第二源气体与化学吸附在半导体衬底的表面上的第一源气体反应，从而通过原子层沉积形成阻挡金属层的一部分。 因此，如果阻挡金属层仅由ALD形成，则沉积速率更大。 在第二实施例中，使用杂质去除气体来除去阻挡金属层中的杂质。 因此，即使将气体供给方案设定为仅使用ALD来制造阻挡金属层，也可以提高成膜速度，而​​不会妨碍阻挡金属层的杂质含量的增加。

公开(公告)号：US06287965B1

公开(公告)日：2001-09-11

申请号：US09511598

申请日：2000-02-23

Applicant: Sang-bom Kang ,  Hyun-seok Lim ,  Yung-sook Chae ,  In-sang Jeon ,  Gil-heyun Choi

Inventor： Sang-bom Kang ,  Hyun-seok Lim ,  Yung-sook Chae ,  In-sang Jeon ,  Gil-heyun Choi

IPC: H01L2144

CPC classification number: H01L21/7687 ,  C23C16/34 ,  C23C16/45529 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76865 ,  H01L28/75

Abstract: A method of forming a metal layer having excellent thermal and oxidation resistant characteristics using atomic layer deposition is provided. The metal layer includes a reactive metal (A), an element (B) for the amorphous combination between the reactive metal (A) and nitrogen (N), and nitrogen (N). The reactive metal (A) may be titanium (Ti), tantalum (Ta), tungsten (W), zirconium (Zr), hafnium (Hf), molybdenum (Mo) or niobium (Nb). The amorphous combination element (B) may be aluminum (Al), silicon (Si) or boron (B). The metal layer is formed by alternately injecting pulsed source gases for the elements (A, B and N) into a chamber according to atomic layer deposition to thereby alternately stack atomic layers. Accordingly, the composition ratio of a nitrogen compound (A—B—N) of the metal layer can be desirably adjusted just by appropriately determining the number of injection pulses of each source gas. According to the composition ratio, a desirable electrical conductivity and resistance of the metal layer can be accurately obtained. The atomic layers are individually deposited, thereby realizing excellent step coverage even in a complex and compact region. A metal layer formed by atomic layer deposition can be employed as a barrier metal layer, a lower electrode or an upper electrode in a semiconductor device.

Abstract translation: 提供了使用原子层沉积形成具有优异的耐热和抗氧化特性的金属层的方法。 金属层包括反应性金属（A），用于反应性金属（A）和氮（N）之间的无定形组合的元素（B）和氮（N））。 反应性金属（A）可以是钛（Ti），钽（Ta），钨（W），锆（Zr），铪（Hf），钼（Mo）或铌（Nb）。 无定形组合元件（B）可以是铝（Al），硅（Si）或硼（B）。 通过根据原子层沉积将元件（A，B和N）的脉冲源气体交替地注入到室中来形成金属层，从而交替堆叠原子层。 因此，通过适当确定各源气体的喷射脉冲数，可以适当地调整金属层的氮化合物（A-B-N）的组成比。 根据组成比，可以准确地获得金属层所需的导电性和电阻。 原子层分别沉积，即使在复杂和紧凑的区域中也能实现优异的阶梯覆盖。 通过原子层沉积形成的金属层可以用作半导体器件中的阻挡金属层，下电极或上电极。

公开(公告)号：US20130052787A1

公开(公告)日：2013-02-28

申请号：US13494328

申请日：2012-06-12

Applicant: Kwang-wook Lee ,  Sang-jun Lee ,  In-seak Hwang ,  In-sang Jeon ,  Byoung-yong Gwak ,  Ho-kyun An

Inventor： Kwang-wook Lee ,  Sang-jun Lee ,  In-seak Hwang ,  In-sang Jeon ,  Byoung-yong Gwak ,  Ho-kyun An

IPC: H01L21/02 ,  H01L21/20

CPC classification number: H01L27/10852 ,  H01L21/76816 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L28/91

Abstract: A method of manufacturing a semiconductor device includes forming a bit line on a substrate comprising an active region; forming an interlayer insulating layer covering the bit line on the substrate; forming a first hole at a location of the active region through the interlayer insulating layer; forming a dummy contact layer by filling the first hole; forming a mold layer on the interlayer insulating layer and the dummy contact layer; forming a second hole at a location of the dummy contact layer through the mold layer; removing the dummy contact layer in the first hole through the second hole; forming an epitaxial layer on a portion of the active region, which is exposed at a lower surface of the first hole; and forming a lower electrode on internal surfaces of the first hole and the second hole.

Abstract translation: 制造半导体器件的方法包括在包括有源区的衬底上形成位线; 形成覆盖所述基板上的所述位线的层间绝缘层; 在有源区的位置通过层间绝缘层形成第一孔; 通过填充第一孔形成虚拟接触层; 在层间绝缘层和虚拟接触层上形成模层; 在所述模拟接触层的位置处通过所述模制层形成第二孔; 通过第二孔去除第一孔中的虚拟接触层; 在所述有源区的在所述第一孔的下表面处露出的部分上形成外延层; 以及在所述第一孔和所述第二孔的内表面上形成下电极。