公开(公告)号：US20150280108A1

公开(公告)日：2015-10-01

申请号：US14741446

申请日：2015-06-16

Applicant: JEONG-HEON PARK ,  KI-WOONG KIM ,  HEE-JU SHIN ,  JOON-MYOUNG LEE ,  WOO-JIN KIM ,  JAE-HOON KIM ,  SE-CHUNG OH ,  YUN-JAE LEE

Inventor： JEONG-HEON PARK ,  KI-WOONG KIM ,  HEE-JU SHIN ,  JOON-MYOUNG LEE ,  WOO-JIN KIM ,  JAE-HOON KIM ,  SE-CHUNG OH ,  YUN-JAE LEE

IPC: H01L43/02 ,  H01L27/22 ,  H01L23/528 ,  H01L43/08

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01F10/30 ,  H01F10/32 ,  H01F10/3254 ,  H01F10/3272 ,  H01L23/528 ,  H01L27/222 ,  H01L43/08 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.

公开(公告)号：US20140021426A1

公开(公告)日：2014-01-23

申请号：US13927090

申请日：2013-06-25

Applicant: Yun-jae LEE ,  Woo-jin KIM ,  Joon-myoung LEE

Inventor： Yun-jae LEE ,  Woo-jin KIM ,  Joon-myoung LEE

IPC: H01L43/02

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A magnetic device comprises a memory cell comprising a magnetic resistance device and lower and upper electrodes with the magnetic resistance device interposed therebetween to apply current to the magnetic resistance device. The magnetic resistance device includes: a buffer layer for controlling a crystalline axis for inducing perpendicular magnetic anisotropy (PMA) in the magnetic resistance device, the buffer layer being in contact with the lower electrode; a seed layer being in contact with the buffer layer and being oriented to a hexagonal close-packed lattice (HCP) (0001) crystal plane; and a perpendicularly magnetized pinned layer being in contact with the seed layer and having an L11 type ordered structure.

Abstract translation: 一种磁性装置包括一个包含一个磁阻装置的存储单元和一个介于它们之间的磁阻装置的下电极和上电极，以向磁阻装置施加电流。 磁阻元件包括：缓冲层，用于控制在磁阻器件中引起垂直磁各向异性（PMA）的晶轴，缓冲层与下电极接触; 种子层与缓冲层接触并取向为六方密堆积晶格（HCP）（0001）晶面; 并且垂直磁化的钉扎层与种子层接触并且具有L11型有序结构。

公开(公告)号：US20170084822A1

公开(公告)日：2017-03-23

申请号：US15169775

申请日：2016-06-01

Applicant: Ki-Woong KIM ,  Ju-Hyun KIM ,  Yong-Sung PARK ,  Se-Chung OH ,  Joon-Myoung LEE

Inventor： Ki-Woong KIM ,  Ju-Hyun KIM ,  Yong-Sung PARK ,  Se-Chung OH ,  Joon-Myoung LEE

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L43/08

CPC classification number: H01L43/10 ,  H01L27/224 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic memory device includes a substrate, a circuit device on the substrate, a lower electrode electrically connected to the circuit device, a magnetic tunnel junction structure (MTJ structure) on the lower electrode, and an upper electrode on the MTJ structure. The MTJ structure includes a pinned layer structure including at least one crystalline ferromagnetic layer and at least one amorphous ferromagnetic layer, a free layer, and a tunnel barrier layer between the pinned layer structure and the free layer.

公开(公告)号：US20150207064A1

公开(公告)日：2015-07-23

申请号：US14505995

申请日：2014-10-03

Applicant: Joon-Myoung LEE ,  Hong-Lae PARK ,  Sang-Yong KIM ,  Woo-Chang LIM

Inventor： Joon-Myoung LEE ,  Hong-Lae PARK ,  Sang-Yong KIM ,  Woo-Chang LIM

IPC: H01L43/12 ,  H01L43/10

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L27/228 ,  H01L43/10

Abstract: A MRAM device may include a fixed layer pattern on a substrate, a first tunnel barrier layer pattern on the fixed layer pattern, a free layer pattern on the first tunnel barrier layer pattern, a second tunnel barrier layer pattern on the free layer pattern, the second tunnel barrier layer pattern including a metal oxide, and a capping layer pattern on the second tunnel barrier layer pattern. The capping layer pattern including a metal may have an oxide layer formation energy lower than the oxide layer formation energy of tantalum.

Abstract translation: MRAM器件可以包括衬底上的固定层图案，固定层图案上的第一隧道势垒层图案，第一隧道势垒层图案上的自由层图案，自由层图案上的第二隧道势垒层图案， 包括金属氧化物的第二隧道势垒层图案和在第二隧道势垒层图案上的覆盖层图案。 包含金属的覆盖层图案可以具有比钽的氧化物层形成能低的氧化层形成能。

公开(公告)号：US09087977B2

公开(公告)日：2015-07-21

申请号：US14254871

申请日：2014-04-16

Applicant: Jeong-Heon Park ,  Ki-Woong Kim ,  Hee-Ju Shin ,  Joon-Myoung Lee ,  Woo-Jin Kim ,  Jae-Hoon Kim ,  Se-Chung Oh ,  Yun-Jae Lee

Inventor： Jeong-Heon Park ,  Ki-Woong Kim ,  Hee-Ju Shin ,  Joon-Myoung Lee ,  Woo-Jin Kim ,  Jae-Hoon Kim ,  Se-Chung Oh ,  Yun-Jae Lee

IPC: H01L43/02 ,  H01L43/08 ,  H01F10/32 ,  G11C11/16

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01F10/30 ,  H01F10/32 ,  H01F10/3254 ,  H01F10/3272 ,  H01L23/528 ,  H01L27/222 ,  H01L43/08 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.

Abstract translation: 提供了具有彼此间隔开的自由层和钉扎层的半导体器件。 在自由层和钉扎层之间形成隧道势垒层。 被钉扎层可以包括下钉扎层和与下钉扎层隔开的上钉扎层。 可以在下钉扎层和上钉扎层之间形成间隔件。 非磁性接合层可以邻近间隔物设置在上或下钉扎层中的层之间。

公开(公告)号：US20180073131A1

公开(公告)日：2018-03-15

申请号：US15629793

申请日：2017-06-22

Applicant: Joon-Myoung LEE ,  Yong-Sung PARK ,  Whan-Kyun KIM ,  Se-Chung OH ,  Young-Man JANG

Inventor： Joon-Myoung LEE ,  Yong-Sung PARK ,  Whan-Kyun KIM ,  Se-Chung OH ,  Young-Man JANG

IPC: C23C14/34 ,  H01J37/32 ,  C23C16/455

CPC classification number: C23C14/34 ,  C23C14/0036 ,  C23C14/0063 ,  C23C14/0068 ,  C23C14/08 ,  C23C14/541 ,  C23C14/566 ,  C23C16/45563 ,  H01J37/3244 ,  H01J37/32715 ,  H01J37/32724 ,  H01J37/34

Abstract: A substrate processing apparatus including a chamber accommodating a substrate; a substrate support in the chamber, the substrate support supporting the substrate; a gas injector to inject an oxidizing gas for oxidizing a metal layer to be disposed on the substrate; a cooler under the substrate to cool the substrate; a target mount disposed on the substrate, the target mount including a target for performing a sputtering process; and a blocker between the target and the gas injector, the blocker shielding the target from the oxidizing gas injected from the gas injector.

公开(公告)号：US20150048464A1

公开(公告)日：2015-02-19

申请号：US14254871

申请日：2014-04-16

Applicant: JEONG-HEON PARK ,  KI-WOONG KIM ,  HEE-JU SHIN ,  JOON-MYOUNG LEE ,  WOO-JIN KIM ,  JAE-HOON KIM ,  SE-CHUNG OH ,  YUN-JAE LEE

Inventor： JEONG-HEON PARK ,  KI-WOONG KIM ,  HEE-JU SHIN ,  JOON-MYOUNG LEE ,  WOO-JIN KIM ,  JAE-HOON KIM ,  SE-CHUNG OH ,  YUN-JAE LEE

IPC: H01L43/02

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01F10/30 ,  H01F10/32 ,  H01F10/3254 ,  H01F10/3272 ,  H01L23/528 ,  H01L27/222 ,  H01L43/08 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.

Abstract translation: 提供了具有彼此间隔开的自由层和钉扎层的半导体器件。 在自由层和钉扎层之间形成隧道势垒层。 被钉扎层可以包括下钉扎层和与下钉扎层隔开的上钉扎层。 可以在下钉扎层和上钉扎层之间形成间隔件。 非磁性接合层可以邻近间隔物设置在上或下钉扎层中的层之间。