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    Semiconductor apparatus
    1.
    发明授权
    Semiconductor apparatus 失效
    半导体装置

    公开(公告)号：US08279702B2

    公开(公告)日：2012-10-02

    申请号：US12840966

    申请日：2010-07-21

    申请人： Jae Bum Ko ,  Sang Jin Byeon

    发明人： Jae Bum Ko ,  Sang Jin Byeon

    IPC分类号： G11C8/00

    CPC分类号： H01L25/0657 ,  G11C8/12 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor apparatus includes an individual-chip-designating-code setting block configured to generate a plurality of sets of individual-chip-designating-codes which have different code values or in which at least two sets of individual-chip-designating-codes have the same code value, in response to a plurality of chip fuse signals; a control block configured to generate a plurality of enable control signals in response to the plurality of chip fuse signals and most significant bits of the plurality of sets of individual-chip-designating-codes; and an individual chip activation block configured to compare individual-chip-designating-codes of the plurality of sets of individual-chip-designating-codes excluding the most significant bits, with chip selection addresses in response to the plurality of enable control signals, and enable one of a plurality of individual-chip-activation-signals depending upon a comparison result.

    摘要翻译： 一种半导体装置，包括单芯片指定码设置块，被配置为生成具有不同码值的多组独立芯片指定码，或者至少两组独立芯片指定码具有 相应的代码值，响应于多个芯片熔丝信号; 控制块，被配置为响应于所述多个芯片熔丝信号和所述多组独立芯片指定代码中的最高有效位而产生多个使能控制信号; 以及单独的芯片激活块，其被配置为响应于所述多个使能控制信号，将所述多个独立芯片指定码组中排除最高有效位的各个芯片指定码与芯片选择地址进行比较，以及 根据比较结果使能多个个别芯片激活信号中的一个。

    SEMICONDUCTOR APPARATUS
    2.
    发明申请
    SEMICONDUCTOR APPARATUS 有权

    公开(公告)号：US20120124408A1

    公开(公告)日：2012-05-17

    申请号：US13166094

    申请日：2011-06-22

    申请人： Sang Jin BYEON ,  Jae Bum Ko

    发明人： Sang Jin BYEON ,  Jae Bum Ko

    IPC分类号： G06F1/06 ,  H01L23/498

    CPC分类号： G11C5/04 ,  G11C16/20 ,  G11C2029/4402 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2924/00014

    摘要： A semiconductor apparatus may comprise: a first chip ID generation unit configured to receive an enable signal through a first through-silicon via and a clock signal through a second through-silicon via and generate a first chip ID signal and a delayed enable signal; a second chip ID generation unit configured to receive the delayed enable signal through a third through-silicon via from the first chip ID generation unit and the clock signal and generate a second chip ID signal; a first chip selection signal generation unit configured to receive the first chip ID signal and a main ID signal and generate a first chip selection signal; and a second chip selection signal generation unit configured to receive the second chip ID signal and the main ID signal and generate a second chip selection signal.

    摘要翻译： 半导体装置可以包括：第一芯片ID生成单元，被配置为通过第一穿通硅通孔接收使能信号和通过第二通过硅通孔的时钟信号，并生成第一芯片ID信号和延迟使能信号; 第二芯片ID生成单元，被配置为通过来自第一芯片ID生成单元的第三通过硅通孔和时钟信号接收延迟使能信号，并生成第二芯片ID信号; 第一芯片选择信号生成单元，被配置为接收第一芯片ID信号和主ID信号，并生成第一芯片选择信号; 以及第二芯片选择信号生成单元，被配置为接收第二芯片ID信号和主ID信号，并生成第二芯片选择信号。

    Semiconductor apparatus
    4.
    发明授权
    Semiconductor apparatus 有权
    半导体装置

    公开(公告)号：US08713349B2

    公开(公告)日：2014-04-29

    申请号：US13166094

    申请日：2011-06-22

    申请人： Sang Jin Byeon ,  Jae Bum Ko

    发明人： Sang Jin Byeon ,  Jae Bum Ko

    IPC分类号： G11C5/06

    CPC分类号： G11C5/04 ,  G11C16/20 ,  G11C2029/4402 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2924/00014

    摘要： A semiconductor apparatus may comprise: a first chip ID generation unit configured to receive an enable signal through a first through-silicon via and a clock signal through a second through-silicon via and generate a first chip ID signal and a delayed enable signal; a second chip ID generation unit configured to receive the delayed enable signal through a third through-silicon via from the first chip ID generation unit and the clock signal and generate a second chip ID signal; a first chip selection signal generation unit configured to receive the first chip ID signal and a main ID signal and generate a first chip selection signal; and a second chip selection signal generation unit configured to receive the second chip ID signal and the main ID signal and generate a second chip selection signal.

    摘要翻译： 半导体装置可以包括：第一芯片ID生成单元，被配置为通过第一穿通硅通孔接收使能信号和通过第二通过硅通孔的时钟信号，并生成第一芯片ID信号和延迟使能信号; 第二芯片ID生成单元，被配置为通过来自第一芯片ID生成单元的第三通过硅通孔和时钟信号接收延迟使能信号，并生成第二芯片ID信号; 第一芯片选择信号生成单元，被配置为接收第一芯片ID信号和主ID信号，并生成第一芯片选择信号; 以及第二芯片选择信号生成单元，被配置为接收第二芯片ID信号和主ID信号，并生成第二芯片选择信号。

    Delay circuit and method for delaying signal
    6.
    发明授权
    Delay circuit and method for delaying signal 有权
    延迟电路和延迟信号的方法

    公开(公告)号：US08344783B2

    公开(公告)日：2013-01-01

    申请号：US12970623

    申请日：2010-12-16

    申请人： Jae Bum Ko ,  Jong Chern Lee ,  Sang Jin Byeon

    发明人： Jae Bum Ko ,  Jong Chern Lee ,  Sang Jin Byeon

    IPC分类号： H03H11/26

    CPC分类号： H03K5/1506 ,  H03K5/05

    摘要： A delay circuit includes: a delay unit configured to receive a clock signal, delay an input signal sequentially by a predetermined time interval, and output a plurality of first delayed signals; and an option unit configured to select one of the plurality of first delayed signals based on one or more select signals, and output a second delayed signal.

    摘要翻译： 延迟电路包括：延迟单元，被配置为接收时钟信号，按预定时间间隔顺序地延迟输入信号，并输出多个第一延迟信号; 以及选择单元，被配置为基于一个或多个选择信号来选择所述多个第一延迟信号中的一个，并输出第二延迟信号。

    SEMICONDUCTOR APPARATUS
    7.
    发明申请
    SEMICONDUCTOR APPARATUS 失效

    公开(公告)号：US20110241763A1

    公开(公告)日：2011-10-06

    申请号：US12840212

    申请日：2010-07-20

    申请人： Jae Bum Ko ,  Sang Jin Byeon

    发明人： Jae Bum Ko ,  Sang Jin Byeon

    IPC分类号： H03K19/003

    CPC分类号： G11C8/12

    摘要： A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating codes which have different code values or at least two of which have the same code value, in response to a plurality of chip fuse signals; and an individual chip activation block configured to compare the plurality of individual chip designating codes with chip selection address in response to the plurality of chip fuse signals, and enable one of a plurality of individual chip activation signals based on a result of the comparison.

    摘要翻译： 半导体装置包括单独的芯片指定代码设置块，其被配置为响应于多个芯片熔丝信号而生成具有不同代码值的多个独立芯片指定代码或其中至少两个具有相同代码值的单独芯片指定代码; 以及单个芯片激活块，其被配置为响应于所述多个芯片熔丝信号来比较所述多个独立芯片指定代码与芯片选择地址，并且基于所述比较的结果来启用多个单独芯片激活信号中的一个。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    8.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 失效
    半导体集成电路

    公开(公告)号：US20110210780A1

    公开(公告)日：2011-09-01

    申请号：US12839333

    申请日：2010-07-19

    申请人： Jae Bum Ko ,  Sang Jin Byeon

    发明人： Jae Bum Ko ,  Sang Jin Byeon

    IPC分类号： H03L5/00

    CPC分类号： G06F1/10

    摘要： A semiconductor integrated circuit includes: a plurality of chips configured to receive an external voltage. Each one of the chips detects a signal delay characteristic of the one of the chips to generate an internal voltage having a level corresponding to the signal delay characteristic.

    摘要翻译： 半导体集成电路包括：被配置为接收外部电压的多个芯片。 每个芯片检测到芯片之一的信号延迟特性，以产生具有与信号延迟特性对应的电平的内部电压。

    Semiconductor apparatus
    9.
    发明授权
    Semiconductor apparatus 失效
    半导体装置

    公开(公告)号：US08400210B2

    公开(公告)日：2013-03-19

    申请号：US12840212

    申请日：2010-07-20

    申请人： Jae Bum Ko ,  Sang Jin Byeon

    发明人： Jae Bum Ko ,  Sang Jin Byeon

    IPC分类号： H03K19/003

    CPC分类号： G11C8/12

    摘要： A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating codes which have different code values or at least two of which have the same code value, in response to a plurality of chip fuse signals; and an individual chip activation block configured to compare the plurality of individual chip designating codes with chip selection address in response to the plurality of chip fuse signals, and enable one of a plurality of individual chip activation signals based on a result of the comparison.

    摘要翻译： 半导体装置包括单独的芯片指定代码设置块，其被配置为响应于多个芯片熔丝信号而生成具有不同代码值的多个独立芯片指定代码或其中至少两个具有相同代码值的单独芯片指定代码; 以及单个芯片激活块，其被配置为响应于所述多个芯片熔丝信号来比较所述多个独立芯片指定代码与芯片选择地址，并且基于所述比较的结果来启用多个单独芯片激活信号中的一个。

    Command buffer circuit of semiconductor apparatus
    10.
    发明授权
    Command buffer circuit of semiconductor apparatus 有权
    半导体装置的指令缓冲电路

    公开(公告)号：US08536904B2

    公开(公告)日：2013-09-17

    申请号：US13217433

    申请日：2011-08-25

    申请人： Jae Bum Ko

    发明人： Jae Bum Ko

    IPC分类号： H03B1/00

    CPC分类号： G11C8/12 ,  G11C8/06

    摘要： A command buffer circuit of a semiconductor apparatus includes a first buffer configured to receive a first command signal and generate a first command control signal, a second buffer configured to receive a second command signal and generate a second command control signal, a second block configured to select and output the first command control signal or the second command control signal in response to a rank control signal, and a control signal generation block configured to generate the rank control signal in response to a single rank signal and a chip select signal.

    摘要翻译： 半导体装置的指令缓冲电路包括配置为接收第一命令信号并产生第一命令控制信号的第一缓冲器，被配置为接收第二命令信号并产生第二命令控制信号的第二缓冲器，被配置为 响应于等级控制信号选择并输出第一命令控制信号或第二命令控制信号，以及控制信号生成块，被配置为响应于单个秩信号和片选信号而产生等级控制信号。