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    Nonvolatile memory device and programming method thereof
    3.
    发明授权
    Nonvolatile memory device and programming method thereof 有权
    非易失性存储器件及其编程方法

    公开(公告)号：US09595333B2

    公开(公告)日：2017-03-14

    申请号：US14702895

    申请日：2015-05-04

    申请人： Jaesung Sim ,  Youngwoo Park

    发明人： Jaesung Sim ,  Youngwoo Park

    IPC分类号： G11C11/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/24 ,  G11C16/04

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/24

    摘要： According to example embodiments, a nonvolatile memory device includes a plurality of cell strings on a horizontal semiconductor layer. Each of the cell strings including a plurality of memory cells stacked in a direction perpendicular to the horizontal semiconductor layer. According to example embodiments, a programming method of the nonvolatile memory device includes setting up bitlines corresponding the cell strings, setting up a plurality of string select lines connected to the cell strings, and applying a negative voltage lower to a ground select line. The ground select line is connected to a plurality of ground select transistors between the memory cells and the semiconductor layer. The string select lines extend in a direction intersecting the bitlines. The negative voltage is lower than a ground voltage.

    摘要翻译： 根据示例性实施例，非易失性存储器件包括在水平半导体层上的多个单元串。 每个单元串包括在与水平半导体层垂直的方向上堆叠的多个存储单元。 根据示例实施例，非易失性存储器件的编程方法包括设置与单元串对应的位线，设置连接到单元串的多个串选择线，以及向接地选择线施加较低的负电压。 接地选择线连接到存储器单元和半导体层之间的多个接地选择晶体管。 字符串选择行在与位线相交的方向上延伸。 负电压低于接地电压。

    Three-dimensional semiconductor memory devices including a vertical channel
    4.
    发明授权
    Three-dimensional semiconductor memory devices including a vertical channel 有权
    包括垂直通道的三维半导体存储器件

    公开(公告)号：US09559115B2

    公开(公告)日：2017-01-31

    申请号：US14644256

    申请日：2015-03-11

    申请人： Jaesung Sim ,  Youngwoo Park

    发明人： Jaesung Sim ,  Youngwoo Park

    IPC分类号： H01L29/10 ,  H01L27/115 ,  H01L29/267 ,  H01L29/165 ,  H01L29/78

    CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/1041 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7827

    摘要： Semiconductor memory devices and methods of forming the semiconductor devices may be provided. The semiconductor memory devices may include a channel portion of an active pillar that may be formed of a semiconductor material having a charge mobility greater than a charge mobility of silicon. The semiconductor devices may also include a non-channel portion of the active pillar including a semiconductor material having a high silicon content.

    摘要翻译： 可以提供半导体存储器件和形成半导体器件的方法。 半导体存储器件可以包括可以由电荷迁移率大于硅的电荷迁移率的半导体材料形成的有源支柱的沟道部分。 半导体器件还可以包括有源柱的非沟道部分，其包括具有高硅含量的半导体材料。

    Semiconductor memory devices including fine patterns and methods of fabricating the same
    5.
    发明授权
    Semiconductor memory devices including fine patterns and methods of fabricating the same 有权
    包括精细图案的半导体存储器件及其制造方法

    公开(公告)号：US09362303B2

    公开(公告)日：2016-06-07

    申请号：US14681505

    申请日：2015-04-08

    申请人： Jaegoo Lee ,  Youngwoo Park ,  Jaeduk Lee

    发明人： Jaegoo Lee ,  Youngwoo Park ,  Jaeduk Lee

    IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L21/768 ,  H01L21/285

    CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/76877 ,  H01L29/66833 ,  H01L29/7926

    摘要： Semiconductor devices are provided including an active pillar protruding from a substrate; a first gate electrode and a second gate electrode adjacent to a sidewall of the active pillar and vertically overlapping with each other, the first and second gate electrodes being insulated from each other; a first intergate insulating layer covering a first surface of the first gate electrode; and a second intergate insulating layer covering a second surface, opposite the first surface, of the second gate electrode and spaced apart from the first intergate insulating layer. The first intergate insulating layer and the second intergate insulating layer define an air gap therebetween.

    摘要翻译： 提供半导体器件，其包括从基板突出的有源柱; 与所述有源柱的侧壁相邻并且彼此垂直重叠的第一栅电极和第二栅电极，所述第一栅电极和所述第二栅电极彼此绝缘; 覆盖所述第一栅电极的第一表面的第一隔间绝缘层; 以及覆盖所述第二栅电极的与所述第一表面相对的第二表面并与所述第一栅极绝缘层间隔开的第二栅极绝缘层。 第一隔间绝缘层和第二隔间绝缘层在其间形成气隙。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US09183893B2

    公开(公告)日：2015-11-10

    申请号：US14037547

    申请日：2013-09-26

    申请人： Kohji Kanamori ,  Youngwoo Park ,  Jintaek Park ,  Kwang Soo Seol ,  Jaeduk Lee

    发明人： Kohji Kanamori ,  Youngwoo Park ,  Jintaek Park ,  Kwang Soo Seol ,  Jaeduk Lee

    IPC分类号： G11C5/06 ,  G11C13/00 ,  H01L45/00 ,  H01L27/22 ,  H01L27/24

    CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C13/0002 ,  G11C13/0023 ,  G11C2213/73 ,  H01L27/222 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

    摘要： According to example embodiments of inventive concepts, a semiconductor memory devices includes: a plurality of memory blocks that each include a plurality of stack structures, global bit lines connected in common to the plurality of memory blocks, block selection lines configured to control electrical connect between the global bit lines and one of the plurality of memory blocks, and vertical selection lines configured to control electrical connected between the global bit lines and one of the plurality of stack structures. Each of the plurality of stack structures includes a plurality of local bit lines, first vertical word lines and second vertical word lines crossing first sidewalls and second sidewalls respectfully of the plurality of stack structures, first variable resistive elements between the plurality of stack structures and the first vertical word lines, and second variable resistive elements between the plurality of stack structures and the second vertical word lines.

    摘要翻译： 根据本发明构思的示例性实施例，半导体存储器件包括：多个存储器块，每个存储块包括多个堆叠结构，共同连接到多个存储器块的全局位线，被配置为控制 全局位线和多个存储器块中的一个以及垂直选择线，其被配置为控制连接在全局位线和多个堆叠结构中的一个之间的电连接。 多个堆叠结构中的每一个包括多个局部位线，第一垂直字线和第二垂直字线，其横向于多个堆叠结构的第一侧壁和第二侧壁相交，多个堆叠结构之间的第一可变电阻元件和 第一垂直字线和第二可变电阻元件在多个堆叠结构和第二垂直字线之间。

    SEMICONDUCTOR DEVICES INCLUDING WORD LINE INTERCONNECTING STRUCTURES
    7.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING WORD LINE INTERCONNECTING STRUCTURES 有权
    包括字线互连结构的半导体器件

    公开(公告)号：US20140306279A1

    公开(公告)日：2014-10-16

    申请号：US14191542

    申请日：2014-02-27

    申请人： Jintaek Park ,  Youngwoo Park ,  Jaeduk Lee

    发明人： Jintaek Park ,  Youngwoo Park ,  Jaeduk Lee

    IPC分类号： H01L23/00 ,  H01L27/115

    CPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

    摘要： A semiconductor memory device includes a substrate including a cell region and an interconnection region, adjacent first and second rows of vertical channels extending vertically from the substrate in the cell region, and layers of word lines stacked on the substrate. Each layer includes a first word line through which the first row of vertical channels passes and a second word line through which the second row of vertical channels passes, and the word lines include respective word line pads extending into the interconnection region. An isolation pattern separates the first and second word lines in the cell region and the interconnection region. First and second pluralities of contact plugs are disposed on opposite sides of the isolation pattern in the interconnection region and contact the word line pads.

    摘要翻译： 半导体存储器件包括：衬底，其包括单元区域和互连区域;相邻的从单元区域中的衬底垂直延伸的第一和第二排垂直沟道以及堆叠在衬底上的字线层。 每层包括第一行垂直通道通过的第一字线和第二行垂直通道通过的第二字线，并且字线包括延伸到互连区域中的相应字线焊盘。 隔离图案分离单元区域和互连区域中的第一和第二字线。 第一和第二多个接触插塞设置在互连区域中的隔离图案的相对侧上，并与字线焊盘接触。

    Three-dimensional semiconductor memory device
    8.
    发明授权
    Three-dimensional semiconductor memory device 有权
    三维半导体存储器件

    公开(公告)号：US08829589B2

    公开(公告)日：2014-09-09

    申请号：US13757273

    申请日：2013-02-01

    申请人： Changhyun Lee ,  Byoungkeun Son ,  Youngwoo Park

    发明人： Changhyun Lee ,  Byoungkeun Son ,  Youngwoo Park

    IPC分类号： H01L29/788 ,  H01L29/04 ,  H01L29/792

    CPC分类号： H01L29/788 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/04 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926

    摘要： A three-dimensional semiconductor memory device may include gap-fill insulating layers extending upward from a substrate, an electrode structure delimited by sidewalls of the gap-fill insulating layers, vertical structures provided between adjacent ones of the gap-fill insulating layers to penetrate the electrode structure, and at least one separation pattern extending along the gap-fill insulating layers and penetrating at least a portion of the electrode structure. The separation pattern may include at least one separation semiconductor layer.

    摘要翻译： 三维半导体存储器件可以包括从衬底向上延伸的间隙填充绝缘层，由间隙填充绝缘层的侧壁限定的电极结构，设置在相邻的间隙填充绝缘层之间的垂直结构以穿透 电极结构，以及沿间隙填充绝缘层延伸并穿透电极结构的至少一部分的至少一个分离图案。 分离图案可以包括至少一个分离半导体层。

    METHODS FOR FORMING ETCH STOP LAYERS, SEMICONDUCTOR DEVICES HAVING THE SAME, AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICES
    9.
    发明申请
    METHODS FOR FORMING ETCH STOP LAYERS, SEMICONDUCTOR DEVICES HAVING THE SAME, AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICES 有权
    形成止蚀层的方法，具有该阻挡层的半导体器件以及用于制造半导体器件的方法

    公开(公告)号：US20140197470A1

    公开(公告)日：2014-07-17

    申请号：US14218091

    申请日：2014-03-18

    申请人： Jaegoo Lee ,  Youngwoo Park

    发明人： Jaegoo Lee ,  Youngwoo Park

    IPC分类号： H01L21/768 ,  H01L27/115

    CPC分类号： H01L21/76832 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

    摘要： A plurality of vertical channels of semiconductor material are formed to extend in a vertical direction through the plurality of insulation layers and the plurality of conductive patterns, a gate insulating layer between the conductive pattern and the vertical channels that insulates the conductive pattern from the vertical channels. Conductive contact regions of the at least two of the conductive patterns are in a stepped configuration. An etch stop layer is positioned on the conductive contact regions, wherein the etch stop layer has a first portion on a first one of the plurality of conductive patterns and has a second portion on a second one of the plurality of conductive patterns, wherein the first portion is of a thickness that is greater than a thickness of the second portion.

    摘要翻译： 多个垂直通道的半导体材料形成为沿着垂直方向延伸穿过多个绝缘层和多个导电图案，导电图案和垂直沟道之间的栅极绝缘层将导电图案与垂直沟道绝缘 。 至少两个导电图案的导电接触区域处于阶梯状结构。 蚀刻停止层位于导电接触区域上，其中蚀刻停止层在多个导电图案中的第一个上具有第一部分，并且在多个导电图案中的第二个导电图案上具有第二部分，其中第一部分 部分的厚度大于第二部分的厚度。

    NONVOLATILE MEMORY INCLUDING MEMORY CELL ARRAY HAVING THREE-DIMENSIONAL STRUCTURE
    10.
    发明申请
    NONVOLATILE MEMORY INCLUDING MEMORY CELL ARRAY HAVING THREE-DIMENSIONAL STRUCTURE 有权
    非易失性存储器，包括具有三维结构的存储器单元阵列

    公开(公告)号：US20140151783A1

    公开(公告)日：2014-06-05

    申请号：US14080823

    申请日：2013-11-15

    申请人： Jintaek Park ,  Youngwoo Park

    发明人： Jintaek Park ,  Youngwoo Park

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/2481 ,  H01L29/4234 ,  H01L29/792

    摘要： A nonvolatile memory is provided which includes a plurality of channel layers and a plurality of insulation layers alternately stacked on a substrate in a direction perpendicular to the substrate, each of the plurality of channel layers including a plurality of channel films extending along a first direction on a plane parallel with the substrate; a plurality of conductive materials extending from a top of the channel layers and the insulation layers up to a portion adjacent to the substrate in a direction perpendicular to the substrate through areas among channel films of each channel layer; a plurality of information storage films provided between the channel films of the channel layers and the conductive materials; and a plurality of bit lines connected to the channel layers, respectively, wherein the conductive materials, the information storage films, and the channel films of the channel layers form a three-dimensional memory cell array, wherein the conductive materials form a plurality of groups, and wherein a distance between the groups is longer than a distance between conductive materials in each other.

    摘要翻译： 提供了一种非易失性存储器，其包括多个通道层和多个绝缘层，所述多个绝缘层沿垂直于所述衬底的方向交替堆叠在衬底上，所述多个沟道层中的每一个包括沿着第一方向延伸的多个沟道膜 与基板平行的平面; 多个导电材料，其从沟道层的顶部和绝缘层延伸到与基板垂直的方向上的与衬底相邻的部分，通过每个沟道层的沟道膜之间的区域; 设置在沟道层的沟道膜和导电材料之间的多个信息存储膜; 以及分别连接到沟道层的多个位线，其中沟道层的导电材料，信息存储膜和沟道膜形成三维存储单元阵列，其中导电材料形成多个组 并且其中所述组之间的距离长于彼此之间的导电材料之间的距离。