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    METAL GATE TRANSISTORS
    1.
    发明申请
    METAL GATE TRANSISTORS 审中-公开
    金属栅极晶体管

    公开(公告)号：US20100102393A1

    公开(公告)日：2010-04-29

    申请号：US12260095

    申请日：2008-10-29

    Applicant: James Yong Meng LEE ,  Jin-Ping HAN ,  Voon-Yew THEAN

    Inventor： James Yong Meng LEE ,  Jin-Ping HAN ,  Voon-Yew THEAN

    IPC: H01L27/092 ,  H01L21/4763

    CPC classification number: H01L21/823807 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

    Abstract: An integrated circuit that includes a substrate having first and second active regions is disclosed. A first transistor of a first type and a second transistor of a second type are disposed in the first and second active regions respectively. Each transistor includes a gate stack having a metal gate electrode over a gate dielectric layer. First and second gate threshold voltage adjusting (GTVA) layers contacting first and second gate dielectric layer of the first and second transistors are provided. The first GTVA layer tunes a gate threshold voltage of the first transistor. A channel of the second transistor includes dopants to tune the gate threshold voltage of the second transistor.

    Abstract translation: 公开了一种包括具有第一和第二有源区的衬底的集成电路。 第一类型的第一晶体管和第二类型的第二晶体管分别设置在第一和第二有源区中。 每个晶体管包括在栅极介电层上方具有金属栅电极的栅极堆叠。 提供了接触第一和第二晶体管的第一和第二栅极介电层的第一和第二栅极阈值电压调节（GTVA）层。 第一GTVA层调谐第一晶体管的栅极阈值电压。 第二晶体管的沟道包括用于调谐第二晶体管的栅极阈值电压的掺杂剂。

    Method of patterning gate electrode with ultra-thin gate dielectric
    5.
    发明授权
    Method of patterning gate electrode with ultra-thin gate dielectric 失效
    用超薄栅极电介质构图栅电极的方法

    公开(公告)号：US06475916B1

    公开(公告)日：2002-11-05

    申请号：US09483936

    申请日：2000-01-18

    Applicant: James Yong Meng Lee ,  Yun Qiang Zhang ,  Chock Hing Gan ,  Ravi Sundaresan

    Inventor： James Yong Meng Lee ,  Yun Qiang Zhang ,  Chock Hing Gan ,  Ravi Sundaresan

    IPC: H01L21302

    CPC classification number: H01L21/28238 ,  H01L21/28211 ,  H01L21/3185 ,  H01L29/66553 ,  H01L29/66583

    Abstract: A new method is provided for the creation of ultra-thin gate oxide layers. Under the first embodiment, sacrificial oxide and nitride are deposited, openings are created in the layer of nitride where the ultra-thin layer of gate oxide is to be created. A layer of poly is deposited over the layer of nitride. The layer of polysilicon is polished, leaving the poly deposited inside the openings. The nitride is removed leaving the gate structure in place overlying the grown gate oxide. Under the second embodiment, sacrificial oxide and nitride are deposited followed by the deposition of TEOS oxide. The layers of TEOS, oxide and nitride are patterned creating openings that expose the surface areas of the layer of sacrificial oxide where the ultra-thin layers of gate oxide are to be grown. A thin conformal layer of nitride is deposited over the structure, this thin layer of conformal nitride is etched to form thin spacers on the sidewalls of the openings in the layers of TEOS oxide and nitride. Pre-gate clean is performed that removes the TEOS oxide and the sacrificial oxide on the bottom of the openings, gate oxidation is performed creating the ultra-thin layers of gate oxide. Poly is deposited, polished back followed by removal of the nitride leaving the poly gate structure in place and overlying the ultra-thin layer of gate oxide.

    Abstract translation: 提供了一种新的制造超薄栅氧化层的方法。 在第一实施例中，沉积牺牲氧化物和氮化物，在氮化物层中产生开口，其中将形成栅极氧化物的超薄层。 一层多晶硅沉积在氮化物层上。 抛光多晶硅层，留下多孔沉积在开口内。 去除氮化物，留下栅极结构覆盖生长的栅极氧化物的位置。 在第二实施例中，沉积牺牲氧化物和氮化物，然后沉积TEOS氧化物。 TEOS，氧化物和氮化物的层被图案化以产生露出氧化物层的表面区域的开口，其中栅极氧化物的超薄层将被生长。 在结构上沉积薄的氮化层保形层，蚀刻该薄层的共形氮化物以在TEOS氧化物和氮化物层中的开口的侧壁上形成薄的间隔物。 进行预栅极清洁，其去除了开口底部的TEOS氧化物和牺牲氧化物，进行栅极氧化，产生栅极氧化物的超薄层。 将Poly沉积，抛光，然后除去留下多晶硅栅结构的氮化物，并覆盖栅极氧化物的超薄层。

    Method to form a recessed source drain on a trench side wall with a replacement gate technique
    7.
    发明授权
    Method to form a recessed source drain on a trench side wall with a replacement gate technique 有权
    用替代栅极技术在沟槽侧壁上形成凹陷源极漏极的方法

    公开(公告)号：US06380088B1

    公开(公告)日：2002-04-30

    申请号：US09764241

    申请日：2001-01-19

    Applicant: Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng

    Inventor： Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng

    IPC: H01L21302

    CPC classification number: H01L29/66583 ,  H01L21/76224 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/4983 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636

    Abstract: An improved MOS transistor and method of making an improved MOS transistor. An MOS transistor having a recessed source drain on a trench sidewall with a replacement gate technique. Holes are formed in the shallow trench isolations, which exposes sidewall of the substrate in the active area. Sidewalls of the substrate are doped in the active area where holes are. Conductive material is then formed in the holes and the conductive material becomes the source and drain regions. The etch stop layer is then removed exposing sidewalls of the conductive material, and oxidizing exposed sidewalls of the conductive material is preformed. Spacers are formed on top of the pad oxide and on the sidewalls of the oxidized portions of the conductive material. The pad oxide layer is removed from the structure but not from under the spacers. A gate dielectric layer is formed on the substrate in the active area between the spacers; and a gate electrode is formed on said gate dielectric layer.

    Abstract translation: 一种改进的MOS晶体管和制造改进的MOS晶体管的方法。 MOS晶体管，具有沟槽侧壁上的凹陷源极漏极，具有替代栅极技术。 在浅沟槽隔离件中形成孔，其在有源区域中暴露衬底的侧壁。 在孔的有源区域中掺杂衬底的侧壁。 然后在孔中形成导电材料，并且导电材料变成源区和漏区。 然后去除蚀刻停止层，暴露导电材料的侧壁，并且对导电材料的暴露侧壁进行氧化预处理。 垫片形成在衬垫氧化物的顶部和导电材料的氧化部分的侧壁上。 衬垫氧化物层从结构中移除，但不从衬垫下方移除。 在间隔物之间​​的有源区域中的基板上形成栅极电介质层; 并且在所述栅极电介质层上形成栅电极。

    Method of patterning gate electrodes with high K gate dielectrics
    8.
    发明授权
    Method of patterning gate electrodes with high K gate dielectrics 有权
    用高K栅极电介质构图栅电极的方法

    公开(公告)号：US06306741B1

    公开(公告)日：2001-10-23

    申请号：US09615809

    申请日：2000-07-13

    Applicant: James Yong Meng Lee ,  Xia Li ,  Yun Qiang Zhang

    Inventor： James Yong Meng Lee ,  Xia Li ,  Yun Qiang Zhang

    IPC: H01L213205

    CPC classification number: H01L21/28202 ,  H01L21/28211 ,  H01L21/28238 ,  H01L21/31116 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66583

    Abstract: A buffer layer and a gate dielectric layer overlying a substrate having at least one active area is provided. A sacrificial oxide layer is formed over the gate dielectric layer. A nitride layer is formed over the sacrificial oxide layer. The nitride layer is patterned to form an opening therein within the active area exposing a portion of the sacrificial oxide layer within the opening. The portion of the sacrificial oxide layer within the opening is stripped, exposing a portion of the underlying gate dielectric layer within the opening. A gate electrode is formed within opening over the portion of the gate dielectric layer. The remaining nitride layer is selectively removed. The remaining sacrificial oxide layer is then stripped and removed.

    Abstract translation: 提供了具有至少一个有效区域的衬底上的缓冲层和栅介质层。 牺牲氧化物层形成在栅极介电层上。 在牺牲氧化物层上形成氮化物层。 图案化氮化物层以在有效区域内形成开口，露出开口内部的牺牲氧化物层的一部分。 剥离开口内的牺牲氧化物层的部分，将下面的栅极介电层的一部分暴露在开口内。 栅极电极形成在栅极电介质层的部分的开口内。 剩余的氮化物层被选择性地去除。 然后剥离并除去剩余的牺牲氧化物层。

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