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    Method of photolithographically forming extremely narrow transistor gate elements
    3.
    发明授权
    Method of photolithographically forming extremely narrow transistor gate elements 有权
    光刻形成极窄晶体管栅极元件的方法

    公开(公告)号：US06762130B2

    公开(公告)日：2004-07-13

    申请号：US10160197

    申请日：2002-05-31

    申请人： Reima Tapani Laaksonen ,  Jarvis B. Jacobs

    发明人： Reima Tapani Laaksonen ,  Jarvis B. Jacobs

    IPC分类号： H01L21302

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32137

    摘要： A method of forming a narrow feature, such as a gate electrode (14) in an integrated circuit is disclosed. A gate layer (14) such as polycrystalline silicon is disposed near a surface of a substrate (12), and a hardmask layer (16) is formed over the gate layer (14). The hardmask layer (16) includes one or more dielectric layers (16a, 16b, 16c) such as silicon-rich silicon nitride, silicon oxynitride, and oxide. Photoresist (18) sensitive to 193 nm UV light is patterned over the hardmask layer (16) to define a feature of a first width (CD) that is reliably patterned at that wavelength. The hardmask layer (16) is then etched to clear from the surface of the gate layer (14). A timed overetch of the hardmask layer (16) reduces hardmask CD and that of the overlying photoresist (18) to the desired feature size. Etch of the gate layer is then carried out to form the desired feature.

    摘要翻译： 公开了一种在集成电路中形成诸如栅电极（14）的窄特征的方法。 诸如多晶硅的栅极层（14）设置在衬底（12）的表面附近，并且在栅极层（14）上形成硬掩模层（16）。 硬掩模层（16）包括一个或多个介电层（16a，16b，16c），例如富硅氮化硅，氮氧化硅和氧化物。 对强度为193nm的紫外光敏感的光致抗蚀剂（18）在硬掩模层（16）上图案化以限定在该波长下可靠地图案化的第一宽度（CD）的特征。 然后蚀刻硬掩模层（16）以从栅极层（14）的表面清除。 硬掩模层（16）的定时过蚀刻将硬掩模CD和上覆光致抗蚀剂（18）的硬掩模CD和硬掩模CD降低到所需的特征尺寸。 然后执行栅极层的蚀刻以形成期望的特征。

    Method and system for forming a transistor having source and drain extensions
    4.
    发明授权
    Method and system for forming a transistor having source and drain extensions 有权
    用于形成具有源极和漏极延伸的晶体管的方法和系统

    公开(公告)号：US06737325B1

    公开(公告)日：2004-05-18

    申请号：US10383322

    申请日：2003-03-06

    申请人： Manoj Mehrotra ,  Reima Tapani Laaksonen

    发明人： Manoj Mehrotra ,  Reima Tapani Laaksonen

    IPC分类号： H01L21366

    CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/28123 ,  H01L21/32137 ,  H01L21/32139

    摘要： According to one embodiment of the invention, a method for manufacturing a transistor is provided. The method includes masking a polysilicon layer of a semiconductor device to have a dimension greater than a critical dimension of a gate to be formed. The polysilicon layer overlies a substrate layer. The method also includes incompletely etching the polysilicon layer. The method also includes forming a source region and a drain region in the substrate layer through the incompletely etched polysilicon layer by doping the substrate layer and applying heat at a first temperature. The method also includes forming a source extension and a drain extension in the substrate layer after forming the source region and the drain region by doping the substrate layer and applying heat at a second temperature.

    摘要翻译： 根据本发明的一个实施例，提供一种制造晶体管的方法。 该方法包括将半导体器件的多晶硅层掩蔽成具有大于要形成的栅极的临界尺寸的尺寸。 多晶硅层覆盖在基底层上。 该方法还包括不完全蚀刻多晶硅层。 该方法还包括通过掺杂衬底层并在第一温度下施加热量，通过未完全蚀刻的多晶硅层在衬底层中形成源极区域和漏极区域。 该方法还包括在通过掺杂衬底层并在第二温度施加热量形成源极区域和漏极区域之后在衬底层中形成源极延伸和漏极延伸。

    Method for forming ultra thin low leakage multi gate devices
    5.
    发明授权
    Method for forming ultra thin low leakage multi gate devices 有权
    用于形成超薄低泄漏多栅极器件的方法

    公开(公告)号：US07459390B2

    公开(公告)日：2008-12-02

    申请号：US11385020

    申请日：2006-03-20

    申请人： Hiroaki Niimi ,  Reima Tapani Laaksonen

    发明人： Hiroaki Niimi ,  Reima Tapani Laaksonen

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/823462 ,  H01L21/823857

    摘要： The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment, includes forming a first layer of gate dielectric material over a semiconductor substrate in a first active region and a second active region of a semiconductor device, and patterning a masking layer to expose the first layer of gate dielectric material located in the first active region. The method further includes subjecting exposed portions of the first layer of gate dielectric material to a nitrogen containing plasma, thereby forming a second layer of gate dielectric material over the first layer of gate dielectric material located in the first active region, incorporating oxygen into the second layer of gate dielectric material located in the first active region, and removing the, patterned masking layer, thereby resulting in a first greater thickness gate dielectric in the first active region and a second lesser thickness gate dielectric in the second active region.

    摘要翻译： 本发明提供一种制造具有多个栅介质厚度层的半导体器件的方法。 在一个实施例中，该方法包括在半导体器件的第一有源区域和第二有源区域中的半导体衬底上形成第一层栅极介电材料层，并且对掩模层进行构图以暴露位于第 在第一个活跃区域。 该方法还包括使第一层栅极电介质材料的暴露部分经受含氮等离子体，由此在位于第一有源区域的第一栅极电介质材料层上形成栅极电介质材料的第二层，将氧合并入第二层 位于第一有源区中的栅介电材料层，以及去除图案化的掩模层，由此在第一有源区中形成第一较大厚度的栅极电介质，并在第二有源区中形成第二较小厚度的栅极电介质。

    Method for forming multi gate devices using a silicon oxide masking layer
    6.
    发明授权
    Method for forming multi gate devices using a silicon oxide masking layer 有权
    使用氧化硅掩蔽层形成多栅极器件的方法

    公开(公告)号：US07799649B2

    公开(公告)日：2010-09-21

    申请号：US11279602

    申请日：2006-04-13

    申请人： Hiroaki Niimi ,  Reima Tapani Laaksonen

    发明人： Hiroaki Niimi ,  Reima Tapani Laaksonen

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823462 ,  Y10S438/981

    摘要： The present invention provides a method for manufacturing a semiconductor device. The method, in one embodiment, includes forming a silicon oxide masking layer over a substrate in a first active region and a second active region of a semiconductor device, patterning the silicon oxide masking layer to expose the substrate in the first active region. The method further includes forming a layer of dielectric material over the substrate in the first active region, the patterned silicon oxide masking layer protecting the substrate from the layer of dielectric material in the second active region.

    摘要翻译： 本发明提供一种制造半导体器件的方法。 在一个实施例中，该方法包括在半导体器件的第一有源区和第二有源区中的衬底上形成氧化硅屏蔽层，图案化氧化硅屏蔽层以暴露第一有源区中的衬底。 该方法还包括在第一有源区中的衬底上形成介电材料层，图案化氧化硅屏蔽层保护衬底免受第二有源区中的介电材料层的影响。

    Method for forming ultra-thin low leakage multiple gate devices using a masking layer over the semiconductor substrate
    7.
    发明授权
    Method for forming ultra-thin low leakage multiple gate devices using a masking layer over the semiconductor substrate 有权
    用于在半导体衬底上形成使用掩模层的超薄低漏多栅极器件的方法

    公开(公告)号：US07670913B2

    公开(公告)日：2010-03-02

    申请号：US11384753

    申请日：2006-03-20

    申请人： Hiroaki Niimi ,  Reima Tapani Laaksonen

    发明人： Hiroaki Niimi ,  Reima Tapani Laaksonen

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823462 ,  H01L21/823857

    摘要： The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment, includes forming a masking layer over a semiconductor substrate in a first active region and a second active region of a semiconductor device, patterning the masking layer to expose the semiconductor substrate in the first active region, and subjecting exposed portions of the semiconductor substrate to a nitrogen containing plasma, thereby forming a first layer of gate dielectric material over the semiconductor substrate in the first active region. The method, in that embodiment, may further include incorporating oxygen into the first layer of gate dielectric material located in the first active region, and then removing the patterned masking layer, and forming a second layer of gate dielectric material over the first layer of gate dielectric material in the first active region and over the semiconductor substrate in the second active region, thereby resulting in a first greater thickness gate dielectric in the first active region and a second lesser thickness gate dielectric in the second active region.

    摘要翻译： 本发明提供一种制造具有多个栅介质厚度层的半导体器件的方法。 在一个实施例中，该方法包括在半导体器件的第一有源区和第二有源区中的半导体衬底上形成掩模层，图案化掩模层以暴露第一有源区中的半导体衬底，并对暴露部分 从而在第一有源区中在半导体衬底上形成第一层栅极电介质材料层。 在该实施例中，该方法还可以包括将氧结合到位于第一有源区中的第一栅极电介质材料层中，然后去除图案化的掩模层，以及在第一层栅极上形成第二层栅极电介质材料层 第一有源区中的介电材料和第二有源区中的半导体衬底上方，从而在第一有源区中形成第一较大厚度的栅极电介质，以及在第二有源区中形成第二较小厚度的栅极电介质。

    Utilizing amorphorization of polycrystalline structures to achieve T-shaped MOSFET gate
    8.
    发明授权
    Utilizing amorphorization of polycrystalline structures to achieve T-shaped MOSFET gate 有权
    利用多晶结构的非晶化实现T型MOSFET栅极

    公开(公告)号：US06482688B2

    公开(公告)日：2002-11-19

    申请号：US09822998

    申请日：2001-03-30

    申请人： Chimin Hu ,  Amitabh Jain ,  Reima Tapani Laaksonen ,  Manoj Mehrotra

    发明人： Chimin Hu ,  Amitabh Jain ,  Reima Tapani Laaksonen ,  Manoj Mehrotra

    IPC分类号： H01L21338

    CPC分类号： H01L21/28114 ,  H01L21/28123

    摘要： A method of forming a generally T-shaped structure. The method comprises forming a poly/amorphous silicon layer stack which comprises a polysilicon layer and a generally amorphous silicon layer overlying the polysilicon layer. The method further comprises selectively etching the poly/amorphous silicon layer stack, wherein an etch rate associated with the generally amorphous silicon layer in an over etch step associated therewith is less than an etch rate associated with the polysilicon layer, thereby causing a lateral portion of the generally amorphous silicon layer to extend beyond a corresponding lateral portion of the polysilicon layer.

    摘要翻译： 形成大致T形结构的方法。 该方法包括形成多晶硅层堆叠，其包括多晶硅层和覆盖多晶硅层的大致非晶硅层。 该方法还包括选择性地蚀刻多晶硅/非晶硅层堆叠，其中在与其相关的过蚀刻步骤中与一般非晶硅层相关联的蚀刻速率小于与多晶硅层相关的蚀刻速率，从而导致 通常非晶硅层延伸超过多晶硅层的对应横向部分。

    Method for controlling a semiconductor manufacturing process
    9.
    发明授权
    Method for controlling a semiconductor manufacturing process 有权
    用于控制半导体制造工艺的方法

    公开(公告)号：US06582973B1

    公开(公告)日：2003-06-24

    申请号：US10117726

    申请日：2002-04-05

    申请人： Reima Tapani Laaksonen ,  Padmanabh Krishnagiri

    发明人： Reima Tapani Laaksonen ,  Padmanabh Krishnagiri

    IPC分类号： H01L2100

    CPC分类号： H01L22/20 ,  H01L21/32137 ,  H01L21/32139

    摘要： A method for dynamically controlling a semiconductor manufacturing process for producing a semiconductor component includes performing a plurality of process segments. Each respective process segment is performed for a respective processing interval. The method includes the steps of: (a) determining a relationship among respective process intervals for at least two particular process segments of the plurality of process segments; (b) determining a first respective process interval required for a first particular process segment to effect a desired result in the semiconductor component; and (c) using the relationship to establish the respective process interval required for at least one selected particular process segment in order to fix the respective process interval for a controlled process segment other than the at least one selected particular process segment.

    摘要翻译： 用于动态地控制用于制造半导体部件的半导体制造工艺的方法包括执行多个处理段。 对于相应的处理间隔执行每个相应的处理段。 该方法包括以下步骤：（a）确定多个处理段中至少两个特定处理段的各过程间隔之间的关系; （b）确定第一特定处理段在半导体组件中实现期望结果所需的第一相应处理间隔; 以及（c）使用所述关系来建立至少一个所选择的特定过程段所需的相应过程间隔，以便固定除了所述至少一个所选择的特定过程段之外的受控过程段的相应过程间隔。