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1.发明申请METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE USING A NITROGEN CONTAINING OXIDE LAYER 有权使用含氮氧化物层制造半导体器件的方法公开(公告)号：US20120028431A1
公开(公告)日：2012-02-02
申请号：US13101860
申请日：2011-05-05
IPC分类号： H01L21/336
CPC分类号： H01L21/28158 , H01L21/28202 , H01L21/28247 , H01L21/823857 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method for forming a semiconductor device, as well as a semiconductor device. The method for manufacturing a semiconductor device, among others, includes providing a gate structure (240) over a substrate (210), the gate structure (240) including a gate electrode (248) located over a nitrided gate dielectric (243), and forming a nitrided region (310) over a sidewall of the nitrided gate dielectric (243).
摘要翻译： 本发明提供一种形成半导体器件的方法以及半导体器件。 制造半导体器件的方法尤其包括在衬底（210）上提供栅极结构（240），所述栅极结构（240）包括位于氮化栅极电介质（243）上方的栅电极（248），以及 在氮化栅极电介质（243）的侧壁上形成氮化区（310）。
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2.发明授权Method for manufacturing a semiconductor device using a nitrogen containing oxide layer 有权使用含氮氧化物层制造半导体器件的方法公开(公告)号：US08802577B2
公开(公告)日：2014-08-12
申请号：US13101860
申请日：2011-05-05
CPC分类号： H01L21/28158 , H01L21/28202 , H01L21/28247 , H01L21/823857 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method for forming a semiconductor device, as well as a semiconductor device. The method for manufacturing a semiconductor device, among others, includes providing a gate structure (240) over a substrate (210), the gate structure (240) including a gate electrode (248) located over a nitrided gate dielectric (243), and forming a nitrided region (310) over a sidewall of the nitrided gate dielectric (243).
摘要翻译： 本发明提供一种形成半导体器件的方法以及半导体器件。 制造半导体器件的方法尤其包括在衬底（210）上提供栅极结构（240），所述栅极结构（240）包括位于氮化栅极电介质（243）上方的栅电极（248），以及 在氮化栅极电介质（243）的侧壁上形成氮化区（310）。
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公开(公告)号：US07459390B2
公开(公告)日：2008-12-02
申请号：US11385020
申请日：2006-03-20
IPC分类号： H01L21/4763
CPC分类号： H01L21/823462 , H01L21/823857
摘要： The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment, includes forming a first layer of gate dielectric material over a semiconductor substrate in a first active region and a second active region of a semiconductor device, and patterning a masking layer to expose the first layer of gate dielectric material located in the first active region. The method further includes subjecting exposed portions of the first layer of gate dielectric material to a nitrogen containing plasma, thereby forming a second layer of gate dielectric material over the first layer of gate dielectric material located in the first active region, incorporating oxygen into the second layer of gate dielectric material located in the first active region, and removing the, patterned masking layer, thereby resulting in a first greater thickness gate dielectric in the first active region and a second lesser thickness gate dielectric in the second active region.
摘要翻译： 本发明提供一种制造具有多个栅介质厚度层的半导体器件的方法。 在一个实施例中，该方法包括在半导体器件的第一有源区域和第二有源区域中的半导体衬底上形成第一层栅极介电材料层，并且对掩模层进行构图以暴露位于第 在第一个活跃区域。 该方法还包括使第一层栅极电介质材料的暴露部分经受含氮等离子体，由此在位于第一有源区域的第一栅极电介质材料层上形成栅极电介质材料的第二层，将氧合并入第二层 位于第一有源区中的栅介电材料层，以及去除图案化的掩模层，由此在第一有源区中形成第一较大厚度的栅极电介质，并在第二有源区中形成第二较小厚度的栅极电介质。
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4.发明授权公开(公告)号：US07799649B2
公开(公告)日：2010-09-21
申请号：US11279602
申请日：2006-04-13
IPC分类号： H01L21/336
CPC分类号： H01L21/823462 , Y10S438/981
摘要： The present invention provides a method for manufacturing a semiconductor device. The method, in one embodiment, includes forming a silicon oxide masking layer over a substrate in a first active region and a second active region of a semiconductor device, patterning the silicon oxide masking layer to expose the substrate in the first active region. The method further includes forming a layer of dielectric material over the substrate in the first active region, the patterned silicon oxide masking layer protecting the substrate from the layer of dielectric material in the second active region.
摘要翻译： 本发明提供一种制造半导体器件的方法。 在一个实施例中，该方法包括在半导体器件的第一有源区和第二有源区中的衬底上形成氧化硅屏蔽层，图案化氧化硅屏蔽层以暴露第一有源区中的衬底。 该方法还包括在第一有源区中的衬底上形成介电材料层，图案化氧化硅屏蔽层保护衬底免受第二有源区中的介电材料层的影响。
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5.发明授权Method for forming ultra-thin low leakage multiple gate devices using a masking layer over the semiconductor substrate 有权用于在半导体衬底上形成使用掩模层的超薄低漏多栅极器件的方法公开(公告)号：US07670913B2
公开(公告)日：2010-03-02
申请号：US11384753
申请日：2006-03-20
IPC分类号： H01L21/336
CPC分类号： H01L21/823462 , H01L21/823857
摘要： The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment, includes forming a masking layer over a semiconductor substrate in a first active region and a second active region of a semiconductor device, patterning the masking layer to expose the semiconductor substrate in the first active region, and subjecting exposed portions of the semiconductor substrate to a nitrogen containing plasma, thereby forming a first layer of gate dielectric material over the semiconductor substrate in the first active region. The method, in that embodiment, may further include incorporating oxygen into the first layer of gate dielectric material located in the first active region, and then removing the patterned masking layer, and forming a second layer of gate dielectric material over the first layer of gate dielectric material in the first active region and over the semiconductor substrate in the second active region, thereby resulting in a first greater thickness gate dielectric in the first active region and a second lesser thickness gate dielectric in the second active region.
摘要翻译： 本发明提供一种制造具有多个栅介质厚度层的半导体器件的方法。 在一个实施例中，该方法包括在半导体器件的第一有源区和第二有源区中的半导体衬底上形成掩模层，图案化掩模层以暴露第一有源区中的半导体衬底，并对暴露部分 从而在第一有源区中在半导体衬底上形成第一层栅极电介质材料层。 在该实施例中，该方法还可以包括将氧结合到位于第一有源区中的第一栅极电介质材料层中，然后去除图案化的掩模层，以及在第一层栅极上形成第二层栅极电介质材料层 第一有源区中的介电材料和第二有源区中的半导体衬底上方，从而在第一有源区中形成第一较大厚度的栅极电介质，以及在第二有源区中形成第二较小厚度的栅极电介质。
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6.发明授权公开(公告)号：US08643113B2
公开(公告)日：2014-02-04
申请号：US12275812
申请日：2008-11-21
IPC分类号： H01L21/70
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/28185 , H01L21/3221 , H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L27/092 , H01L27/11 , H01L29/401 , H01L29/42364 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/7833
摘要： A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed.
摘要翻译： 公开了一种用于在PMOS金属栅中的氧和NMOS栅极中的金属原子富集的NMOS和PMOS晶体管形成金属替代栅极的工艺，使得PMOS栅极具有高于4.85eV的有效功函数，并且NMOS栅极具有以下有效的功函数 4.25 eV。 NMOS和PMOS栅极中的金属功函数层被氧化，以将它们的有效功函数增加到期望的PMOS范围。 在PMOS栅极上形成氧扩散阻挡层，在NMOS栅极上形成氧吸气剂。 吸气剂退火从NMOS功能层提取氧气，并将金属原子富集添加到NMOS功能层，将其有效功函数降低到所需的NMOS范围。 公开了金属加工功能层的工艺和材料，氧化工艺和吸氧剂。
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7.发明申请Method of Substantially Reducing the Formation of SiGe Abnormal Growths on Polycrystalline Electrodes for Strained-Channel PMOS Transistors 有权用于应变通道PMOS晶体管的多结晶电极上SiGe异常生长形成的方法公开(公告)号：US20140017866A1
公开(公告)日：2014-01-16
申请号：US13550494
申请日：2012-07-16
IPC分类号： H01L21/336 , H01L21/283
CPC分类号： H01L29/7848 , H01L21/28035 , H01L21/3211 , H01L21/32139 , H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834
摘要： The likelihood of forming silicon germanium abnormal growths, which can be undesirably formed on the gate electrode of a strained-channel PMOS transistor at the same time that silicon germanium source and drain regions are formed, is substantially reduced by using protection materials that reduce the likelihood that the gate electrode is exposed during the formation of the silicon germanium source and drain regions.
摘要翻译： 在形成硅锗源极和漏极区域的同时，可能不期望地形成在应变通道PMOS晶体管的栅电极上形成硅锗异常生长的可能性通过使用降低可能性的保护材料而大大减少 在形成硅锗源极和漏极区域期间，栅电极被暴露。
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8.发明授权Method to maximize nitrogen concentration at the top surface of gate dielectrics 有权最大化栅极电介质顶表面的氮浓度的方法公开(公告)号：US08198184B2
公开(公告)日：2012-06-12
申请号：US12570620
申请日：2009-09-30
IPC分类号： H01L29/78 , H01L21/336 , H01L21/314
CPC分类号： H01L21/28202 , H01L21/3145 , H01L21/3185 , H01L29/4916 , H01L29/518 , H01L29/7833
摘要： An integrated circuit having a gate dielectric layer (414, 614, 814) having an improved nitrogen profile and a method of fabrication. The gate dielectric layer is a graded layer with a significantly higher nitrogen concentration at the electrode surface than near the substrate surface. An amorphous silicon layer (406) may be deposited prior to nitridation to retain the nitrogen concentration at the top surface (416). Alternatively, a thin silicon nitride layer (610) may be deposited after anneal or a wet nitridation process may be performed.
摘要翻译： 一种具有具有改进的氮分布的栅介电层（414,614,814）和一种制造方法的集成电路。 栅极电介质层是在电极表面处的氮浓度显着高于衬底表面附近的梯度层。 可以在氮化之前沉积非晶硅层（406）以将氮浓度保持在顶表面（416）。 或者，可以在退火之后沉积薄氮化硅层（610），或者可以执行湿式氮化处理。
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9.发明申请公开(公告)号：US20110120374A1
公开(公告)日：2011-05-26
申请号：US13017828
申请日：2011-01-31
申请人： Malcolm J. Bevan , Haowen Bu , Hiroaki Niimi , Husam N. Alshareef
发明人： Malcolm J. Bevan , Haowen Bu , Hiroaki Niimi , Husam N. Alshareef
IPC分类号： H01L21/469
CPC分类号： H01L21/28158 , C23C16/45557 , C23C16/4582 , H01J37/32752 , H01J37/32825 , H01J37/32899 , H01J2237/3321 , H01L21/02181 , H01L21/0223 , H01L21/02255 , H01L21/02318 , H01L21/02323 , H01L21/02326 , H01L21/02329 , H01L21/02332 , H01L21/0234 , H01L21/28035 , H01L21/28167 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28229 , H01L21/3105 , H01L21/31604 , H01L21/318 , H01L21/3205 , H01L21/324 , H01L21/67161 , H01L21/67167 , H01L21/67196 , H01L21/67201 , H01L21/6776 , H01L29/42364 , H01L29/4908 , H01L29/4916 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66477 , H01L29/78
摘要： Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.
摘要翻译： 可以减少在制造栅极电介质结构中使用的工艺之间发生的栅极介电层的氧化物生长。 氧化物生长的减少可以通过将栅极电介质层保持在有效的方式来实现，以在制造栅极电介质结构中的至少两个顺序的工艺步骤之间减轻栅极电介质层的氧化物生长。 维持栅极电介质层在有效减少氧化物生长的环境中也改善了注入栅电介质的氮的均匀性。
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10.发明申请STRUCTURE AND METHOD FOR METAL GATE STACK OXYGEN CONCENTRATION CONTROL USING AN OXYGEN DIFFUSION BARRIER LAYER AND A SACRIFICIAL OXYGEN GETTERING LAYER 有权使用氧气扩散障碍层和极性氧气捕获层的金属栅极氧化浓度控制的结构和方法公开(公告)号：US20100127336A1
公开(公告)日：2010-05-27
申请号：US12275812
申请日：2008-11-21
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/28185 , H01L21/3221 , H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L27/092 , H01L27/11 , H01L29/401 , H01L29/42364 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/7833
摘要： A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed.
摘要翻译： 公开了一种用于在PMOS金属栅中的氧和NMOS栅极中的金属原子富集的NMOS和PMOS晶体管形成金属替代栅极的工艺，使得PMOS栅极具有高于4.85eV的有效功函数，并且NMOS栅极具有以下有效的功函数 4.25 eV。 NMOS和PMOS栅极中的金属功函数层被氧化，以将它们的有效功函数增加到期望的PMOS范围。 在PMOS栅极上形成氧扩散阻挡层，在NMOS栅极上形成氧吸气剂。 吸气剂退火从NMOS功能层提取氧气，并将金属原子富集添加到NMOS功能层，将其有效功函数降低到所需的NMOS范围。 公开了金属加工功能层的工艺和材料，氧化工艺和吸氧剂。
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