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14 条记录 (耗时 0.013 秒)

    Controlled clock phase generation
    1.
    发明授权
    Controlled clock phase generation 有权
    控制时钟相位生成

    公开(公告)号：US08258837B2

    公开(公告)日：2012-09-04

    申请号：US12640842

    申请日：2009-12-17

    申请人： Praveen Mosalikanti ,  Nasser Kurd

    发明人： Praveen Mosalikanti ,  Nasser Kurd

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0805 ,  H03K5/133 ,  H03K5/15 ,  H03K2005/00032 ,  H03K2005/00104 ,  H03L7/0812 ,  H03L7/0816

    摘要： Methods and systems to generate multiple phases of a clock may include a delay locked loop (DLL) to generate a bias signal to control a delay time through DLL delay elements in response to a first clock, and a plurality of a quadrature slave delay lines (SDLs), each to generate a plurality of successively phase shifted clocks over a quadrant of a corresponding selected phase of a second clock. The SDLs may be biased with the DLL bias signal to control phase differences between the generated clocks. One or more phase interpolators, such as contention based phase interpolators, may be coupled to outputs of each SDL. A frequency of the second clock may be equal to or greater than a frequency of the first clock. The SDLs may be implemented with fewer delay elements than the DLL.

    摘要翻译： 用于产生时钟的多个相位的方法和系统可以包括延迟锁定环（DLL），以产生偏置信号，以响应于第一时钟来控制通过DLL延迟元件的延迟时间，以及多个正交从属延迟线 SDL），其每一个在第二时钟的相应选择的相位的象限上产生多个连续相移的时钟。 SDL可以用DLL偏置信号偏置来控制所产生的时钟之间的相位差。 一个或多个相位内插器，例如基于竞争的相位内插器，可以耦合到每个SDL的输出。 第二时钟的频率可以等于或大于第一时钟的频率。 SDL可以用比DLL更少的延迟元件来实现。

    Method and apparatus for power consumption reduction
    6.
    发明申请
    Method and apparatus for power consumption reduction 有权
    降低功耗的方法和装置

    公开(公告)号：US20050102642A1

    公开(公告)日：2005-05-12

    申请号：US10703562

    申请日：2003-11-10

    申请人： James Tschanz ,  Nasser Kurd ,  Javed Barkatullah ,  Vivek De

    发明人： James Tschanz ,  Nasser Kurd ,  Javed Barkatullah ,  Vivek De

    IPC分类号： G06F9/45 ,  G06F17/50

    CPC分类号： G06F17/5045

    摘要： A method and chip design are provided for reducing power consumption. A first functional block having a phase logic circuit may be provided in a first area of a chip. A second functional block having an edge-triggered circuit may be provided in a second area of the chip. Edge-triggered circuits within the second functional block may be replaced with dual edge-triggered circuits. Phase logic circuits may be clocked by a full frequency clock signal and dual edge-triggered circuits may be clocked by a half-frequency clock signal.

    摘要翻译： 提供了一种降低功耗的方法和芯片设计。 具有相位逻辑电路的第一功能块可以设置在芯片的第一区域中。 具有边缘触发电路的第二功能块可以设置在芯片的第二区域中。 第二功能块内的边沿触发电路可以用双边沿触发电路代替。 相位逻辑电路可以由全频时钟信号来计时，并且双边沿触发电路可以由半频时钟信号来计时。

    Apparatus, system, and method for re-synthesizing a clock signal
    7.
    发明授权
    Apparatus, system, and method for re-synthesizing a clock signal 有权
    用于重新合成时钟信号的装置，系统和方法

    公开(公告)号：US09190991B2

    公开(公告)日：2015-11-17

    申请号：US13993137

    申请日：2011-12-15

    申请人： Mark Neidengard ,  Vaughn Grossnickle ,  Nasser Kurd ,  Jeffrey Krieger

    发明人： Mark Neidengard ,  Vaughn Grossnickle ,  Nasser Kurd ,  Jeffrey Krieger

    IPC分类号： H03K3/017 ,  H03K5/04 ,  G06F1/04

    CPC分类号： H03K5/04 ,  G06F1/04

    摘要： Described herein are apparatus, method, and system for re-synthesizing a clock signal. The apparatus comprises: a first logic unit to detect a rising edge of an input clock signal and for generating a rising edge of an output clock signal based on the detected rising edge of the input clock signal, the input clock signal having a non-50% duty cycle and a first period; and a second logic unit to compute a falling edge of the output clock signal according to the detected rising edge of the input clock signal, the falling edge of the output clock signal being near half of the first period.

    摘要翻译： 这里描述了用于重新合成时钟信号的装置，方法和系统。 该装置包括：第一逻辑单元，用于检测输入时钟信号的上升沿，并且用于基于检测到的输入时钟信号的上升沿产生输出时钟信号的上升沿，所述输入时钟信号具有非50 占空比的百分之一和第一期; 以及第二逻辑单元，用于根据检测到的输入时钟信号的上升沿计算输出时钟信号的下降沿，输出时钟信号的下降沿接近第一周期的一半。

    DIGITAL QUADRATURE PHASE CORRECTION
    8.
    发明申请
    DIGITAL QUADRATURE PHASE CORRECTION 有权
    数字相位校正

    公开(公告)号：US20110148498A1

    公开(公告)日：2011-06-23

    申请号：US12640763

    申请日：2009-12-17

    申请人： Praveen Mosalikanti ,  Nasser Kurd

    发明人： Praveen Mosalikanti ,  Nasser Kurd

    IPC分类号： H03H11/16

    CPC分类号： H03H17/08

    摘要： Methods and systems to adjust a phase difference between signals, such as to perform quadrature phase correction. First and second signals are digitally compared, such as with exclusive OR circuitry, to provide a comparison signal having a duty cycle representative of a phase difference between the signals. A phase delay of one or both of the first and second signals is adjusted until the duty cycle of the comparison signal corresponds to a desired phase difference. In a clock and data recovery system, the signals may correspond to a zero degree phase of a first phase interpolator and a ninety degree phase of a second phase interpolator, and digital codes to the first and second phase interpolators may be adjusted to provide a fifty percent duty cycle in the comparison signal.

    摘要翻译： 调整信号之间的相位差的方法和系统，例如执行正交相位校正。 数字比较第一和第二信号，例如用异或电路，以提供具有表示信号之间的相位差的占空比的比较信号。 调整第一和第二信号中的一个或两个的相位延迟，直到比较信号的占空比对应于期望的相位差。 在时钟和数据恢复系统中，信号可以对应于第一相位内插器的零度相位和第二相位内插器的九十度相位，并且可以调整到第一和第二相位内插器的数字代码以提供五十 百分比占空比在比较信号中。

    Method and apparatus for power consumption reduction
    9.
    发明申请
    Method and apparatus for power consumption reduction 失效
    降低功耗的方法和装置

    公开(公告)号：US20060259890A1

    公开(公告)日：2006-11-16

    申请号：US11486030

    申请日：2006-07-14

    申请人： James Tschanz ,  Nasser Kurd ,  Javed Barkatullah ,  Vivek De

    发明人： James Tschanz ,  Nasser Kurd ,  Javed Barkatullah ,  Vivek De

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： A method and chip design are provided for reducing power consumption. A first functional block having a phase logic circuit may be provided in a first area of a chip. A second functional block having an edge-triggered circuit may be provided in a second area of the chip. Edge-triggered circuits within the second functional block may be replaced with dual edge-triggered circuits. Phase logic circuits may be clocked by a full frequency clock signal and dual edge-triggered circuits may be clocked by a half-frequency clock signal.

    摘要翻译： 提供了一种降低功耗的方法和芯片设计。 具有相位逻辑电路的第一功能块可以设置在芯片的第一区域中。 具有边缘触发电路的第二功能块可以设置在芯片的第二区域中。 第二功能块内的边沿触发电路可以用双边沿触发电路代替。 相位逻辑电路可以由全频时钟信号来计时，并且双边沿触发电路可以由半频时钟信号来计时。

    Digital quadrature phase correction
    10.
    发明授权
    Digital quadrature phase correction 有权
    数字正交相位校正

    公开(公告)号：US08552781B2

    公开(公告)日：2013-10-08

    申请号：US12640763

    申请日：2009-12-17

    申请人： Praveen Mosalikanti ,  Nasser Kurd

    发明人： Praveen Mosalikanti ,  Nasser Kurd

    IPC分类号： H03K3/00 ,  H03K5/13 ,  H03H11/16

    CPC分类号： H03H17/08

    摘要： Methods and systems to adjust a phase difference between signals, such as to perform quadrature phase correction. First and second signals are digitally compared, such as with exclusive OR circuitry, to provide a comparison signal having a duty cycle representative of a phase difference between the signals. A phase delay of one or both of the first and second signals is adjusted until the duty cycle of the comparison signal corresponds to a desired phase difference. In a clock and data recovery system, the signals may correspond to a zero degree phase of a first phase interpolator and a ninety degree phase of a second phase interpolator, and digital codes to the first and second phase interpolators may be adjusted to provide a fifty percent duty cycle in the comparison signal.

    摘要翻译： 调整信号之间的相位差的方法和系统，例如执行正交相位校正。 数字比较第一和第二信号，例如用异或电路，以提供具有表示信号之间的相位差的占空比的比较信号。 调整第一和第二信号中的一个或两个的相位延迟，直到比较信号的占空比对应于期望的相位差。 在时钟和数据恢复系统中，信号可以对应于第一相位内插器的零度相位和第二相位内插器的九十度相位，并且可以调整到第一和第二相位内插器的数字代码以提供五十 百分比占空比在比较信号中。