公开(公告)号：US09143144B2

公开(公告)日：2015-09-22

申请号：US14005887

申请日：2012-03-19

申请人： Jayanth Kuppambatti ,  Junhua Shen ,  Peter Kinget

发明人： Jayanth Kuppambatti ,  Junhua Shen ,  Peter Kinget

IPC分类号： H03M1/12 ,  H03M1/00 ,  G06F1/08 ,  H03M1/44

CPC分类号： H03M1/002 ,  G06F1/08 ,  H03M1/1245 ,  H03M1/442

摘要： Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage.

摘要翻译： 系统包括：第一MDAC级，包括：基于输入信号输出值的子ADC; 至少两个被充电到Vref的参考电容器; 至少两个采样电容器被充电到Vin; 以及多个开关，其耦合所述至少两个参考电容器，使得它们在采样阶段被充电，所述至少两个采样电容器耦合所述至少两个采样电容器，使得它们在采样阶段期间被充电，所述至少两个采样电容器将至少一个参考电容器 使得其在保持阶段期间平行于所述至少两个采样电容器中的一个，并且耦合所述至少两个采样电容器中的另一个，使得其耦合至少一个参考电容器和至少一个采样电容器 两个采样电容器到第二MDAC级的参考电容器。

公开(公告)号：US20160013803A1

公开(公告)日：2016-01-14

申请号：US14860074

申请日：2015-09-21

申请人： Jayanth Kuppambatti ,  Junhua Shen ,  Peter Kinget

发明人： Jayanth Kuppambatti ,  Junhua Shen ,  Peter Kinget

IPC分类号： H03M1/00 ,  H03M1/44 ,  H03M1/12

CPC分类号： H03M1/002 ,  G06F1/08 ,  H03M1/1245 ,  H03M1/442

摘要： Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage.

摘要翻译： 系统包括：第一MDAC级，包括：基于输入信号输出值的子ADC; 至少两个被充电到Vref的参考电容器; 至少两个采样电容器被充电到Vin; 以及多个开关，其耦合所述至少两个参考电容器，使得它们在采样阶段被充电，所述至少两个采样电容器耦合所述至少两个采样电容器，使得它们在采样阶段期间被充电，所述至少两个采样电容器将至少一个参考电容器 使得其在保持阶段期间平行于所述至少两个采样电容器中的一个，并且耦合所述至少两个采样电容器中的另一个，使得其耦合至少一个参考电容器和至少一个采样电容器 两个采样电容器到第二MDAC级的参考电容器。

公开(公告)号：US10084414B2

公开(公告)日：2018-09-25

申请号：US15021620

申请日：2014-09-15

申请人： THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK ,  Baradwaj Vigraham ,  Jayanth Kuppambatti ,  Peter R. Kinget

发明人： Baradwaj Vigraham ,  Jayanth Kuppambatti ,  Peter R. Kinget

IPC分类号： H03F3/38 ,  H03F1/26 ,  H03K3/017 ,  H03F3/217 ,  H03F3/45 ,  H03K3/037 ,  H03K5/24

CPC分类号： H03F1/26 ,  H03F3/217 ,  H03F3/2173 ,  H03F3/45636 ,  H03F2200/264 ,  H03F2200/351 ,  H03F2203/45288 ,  H03K3/017 ,  H03K3/037 ,  H03K5/24

摘要： Circuits and methods for switched mode operational amplifiers are provided. In some embodiments, circuits are provided, the circuits comprising: an amplifier having an output; a first pulse width modulator (PWM) having an input coupled to the output of the amplifier and using a first periodic reference signal waveform; and a second PWM having an input coupled to the output of the amplifier and using a second periodic reference signal waveform, wherein the second periodic reference signal waveform is 180 degrees out of phase from the first periodic reference signal waveform. In some embodiments, circuits are provided, the circuits comprising: an amplifier having an output; and a plurality of pulse width modulators (PWMs) each having an input coupled to the output of the amplifier and using a corresponding unique one of a plurality of periodic reference signal waveforms, wherein the plurality of periodic reference signal waveforms are shifted in phase.

公开(公告)号：US20160269044A1

公开(公告)日：2016-09-15

申请号：US15025111

申请日：2014-09-29

申请人： Jayanth KUPPAMBATTI ,  Baradwaj VIGRAHAM ,  Peter R. KINGET ,  THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK

发明人： Jayanth Kuppambatti ,  Baradwaj Vigraham ,  Peter R. Kinget

IPC分类号： H03M3/00

CPC分类号： H03M3/464 ,  H03M3/338 ,  H03M3/388

摘要： Circuits, methods, and media for providing calibrated delta-sigma modulators are provided. In some embodiments, circuits for a delta-sigma modulator are provided, the circuits comprising: an analog-to-digital converter that produces an output having multiple bits; a digital-to-analog converter having an input having multiple bits; a switch coupled between the output the input that can be used to configure connections between the bits of the output and the bits of the input; a hardware processor that: for multiple iterations, sets a configuration of the switch, samples the bits of the output to produce sample values for each bit of the bits of the output, and calculates an average of the sample values for each of the bits of the output values; computes weights for each of the bits of the output values; and calculates weighted output values for every value of the outputs.

摘要翻译： 提供了用于提供校准的Δ-Σ调制器的电路，方法和介质。 在一些实施例中，提供了用于Δ-Σ调制器的电路，所述电路包括：产生具有多个位的输出的模数转换器; 具有具有多个位的输入的数模转换器; 耦合在输出端之间的开关，输入端可用于配置输出位和输入位之间的连接; 硬件处理器：对于多次迭代，设置开关的配置，对输出的比特进行采样以产生输出的比特的每个比特的采样值，并且计算每个比特的采样值的平均值 输出值; 计算输出值的每个位的权重; 并计算输出的每个值的加权输出值。

公开(公告)号：US20160226451A1

公开(公告)日：2016-08-04

申请号：US15021620

申请日：2014-09-15

申请人： Baradwaj VIGRAHAM ,  Jayanth KUPPAMBATTI ,  Peter, R. KINGET ,  The Trustees of Columbia University in the City of New York

发明人： Baradwaj Vigraham ,  Jayanth Kuppambatti ,  Peter R. Kinget

IPC分类号： H03F1/26 ,  H03F3/45 ,  H03F3/217 ,  H03K3/037 ,  H03K5/24

CPC分类号： H03F1/26 ,  H03F3/217 ,  H03F3/2173 ,  H03F3/45636 ,  H03F2200/264 ,  H03F2200/351 ,  H03F2203/45288 ,  H03K3/017 ,  H03K3/037 ,  H03K5/24

摘要： Circuits and methods for switched mode operational amplifiers are provided. In some embodiments, circuits are provided, the circuits comprising: an amplifier having an output; a first pulse width modulator (PWM) having an input coupled to the output of the amplifier and using a first periodic reference signal waveform; and a second PWM having an input coupled to the output of the amplifier and using a second periodic reference signal waveform, wherein the second periodic reference signal waveform is 180 degrees out of phase from the first periodic reference signal waveform. In some embodiments, circuits are provided, the circuits comprising: an amplifier having an output; and a plurality of pulse width modulators (PWMs) each having an input coupled to the output of the amplifier and using a corresponding unique one of a plurality of periodic reference signal waveforms, wherein the plurality of periodic reference signal waveforms are shifted in phase.

摘要翻译： 提供了开关模式运算放大器的电路和方法。 在一些实施例中，提供电路，所述电路包括：具有输出的放大器; 第一脉冲宽度调制器（PWM），其具有耦合到放大器的输出并使用第一周期性参考信号波形的输入; 以及第二PWM，具有耦合到所述放大器的输出并使用第二周期性参考信号波形的输入，其中所述第二周期性参考信号波形与所述第一周期性参考信号波形相差180度。 在一些实施例中，提供电路，所述电路包括：具有输出的放大器; 以及多个脉冲宽度调制器（PWM），每个脉冲宽度调制器（PWM）具有耦合到放大器的输出的输入并且使用多个周期性参考信号波形中的相应唯一的脉冲宽度调制器（PWM），其中多个周期性参考信号波形同相位移。

公开(公告)号：US20140197971A1

公开(公告)日：2014-07-17

申请号：US14005887

申请日：2012-03-19

申请人： Jayanth Kuppambatti ,  Junhua Shen ,  Peter Kinget

发明人： Jayanth Kuppambatti ,  Junhua Shen ,  Peter Kinget

IPC分类号： H03M1/00

CPC分类号： H03M1/002 ,  G06F1/08 ,  H03M1/1245 ,  H03M1/442

摘要： Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage.

摘要翻译： 系统包括：第一MDAC级，包括：基于输入信号输出值的子ADC; 至少两个被充电到Vref的参考电容器; 至少两个采样电容器被充电到Vin; 以及多个开关，其耦合所述至少两个参考电容器，使得它们在采样阶段被充电，所述至少两个采样电容器耦合所述至少两个采样电容器，使得它们在采样阶段期间被充电，所述至少两个采样电容器将至少一个参考电容器 使得其在保持阶段期间平行于所述至少两个采样电容器中的一个，并且耦合所述至少两个采样电容器中的另一个，使得其耦合至少一个参考电容器和至少一个采样电容器 两个采样电容器到第二MDAC级的参考电容器。