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公开(公告)号:US20070120216A1
公开(公告)日:2007-05-31
申请号:US11164653
申请日:2005-11-30
CPC分类号: H01L23/53214 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05093 , H01L2224/05554 , H01L2224/05572 , H01L2224/05624 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/16 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48624 , H01L2224/48699 , H01L2224/48724 , H01L2224/48799 , H01L2224/48824 , H01L2924/0001 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01042 , H01L2924/01046 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00014 , H01L2924/00
摘要: A structure and a method of forming the structure. The structure including: an integrated circuit chip having a set of wiring levels from a first wiring level to a last wiring level, each wiring level including one or more damascene, dual-damascene wires or damascene vias embedded in corresponding interlevel dielectric levels, a top surface of a last damascene or dual-damascene wire of the last wiring level substantially coplanar with a top surface of a corresponding last interlevel dielectric level; a capping layer in direct physical and electrical contact with a top surface of the last damascene or dual-damascene wire, the last damascene or dual-damascene wire comprising copper; a dielectric passivation layer formed on a top surface of the last interlevel dielectric level; and an aluminum pad in direct physical and electrical contact with the capping layer, a top surface of the aluminum pad not covered by the dielectric passivation layer.
摘要翻译: 一种形成结构的结构和方法。 该结构包括:集成电路芯片,其具有从第一布线级别到最后布线级别的布线级别的集合,每个布线级别包括嵌入在相应的层间电介质层中的一个或多个镶嵌,双镶嵌线或镶嵌孔,顶部 最后一个镶嵌层或最后布线层的双镶嵌线的表面与相应的最后层间介电层的顶表面基本共面; 与最后的镶嵌或双镶嵌线的顶表面直接物理和电接触的封盖层,包括铜的最后镶嵌或双镶嵌线; 形成在最后层间电介质层的顶表面上的电介质钝化层; 以及与覆盖层直接物理和电接触的铝焊盘,铝焊盘的顶表面未被电介质钝化层覆盖。