公开(公告)号：US20170288634A1

公开(公告)日：2017-10-05

申请号：US15408730

申请日：2017-01-18

申请人： DAE-WOON KANG ,  Jeong-Don IHM ,  Byung-Hoon JEONG ,  Young-Don CHOI

发明人： DAE-WOON KANG ,  Jeong-Don IHM ,  Byung-Hoon JEONG ,  Young-Don CHOI

IPC分类号： H03H7/38 ,  G11C16/10 ,  G11C16/08 ,  G11C16/26

CPC分类号： H03H7/38 ,  G11C5/025 ,  G11C5/04 ,  G11C7/1057 ,  G11C7/1084 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008 ,  G11C2207/105 ,  H03K19/0005 ,  H03K19/017545

摘要： A nonvolatile memory device includes a first memory structure. The first memory structure includes first through N-th memory dies that may be connected to an external memory controller via a first channel. N is a natural number equal to or greater than two. At least one of the first through N-th memory dies is configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies.

公开(公告)号：US10205431B2

公开(公告)日：2019-02-12

申请号：US15408730

申请日：2017-01-18

申请人： Dae-Woon Kang ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

发明人： Dae-Woon Kang ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC分类号： H03K19/0175 ,  G11C7/00 ,  H03H7/38 ,  H03K19/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C5/02 ,  G11C5/04 ,  G11C7/10 ,  G11C29/02 ,  G11C16/04 ,  G11C29/50

摘要： A nonvolatile memory device includes a first memory structure. The first memory structure includes first through N-th memory dies that may be connected to an external memory controller via a first channel. N is a natural number equal to or greater than two. At least one of the first through N-th memory dies is configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies.

公开(公告)号：US10176878B2

公开(公告)日：2019-01-08

申请号：US15452885

申请日：2017-03-08

申请人： Jeong-don Ihm ,  Siddharth Katare ,  Hyun-jin Kim

发明人： Jeong-don Ihm ,  Siddharth Katare ,  Hyun-jin Kim

IPC分类号： G11C16/28 ,  G11C16/04 ,  G11C7/06 ,  G11C7/12 ,  G11C16/24 ,  H01L27/11582

摘要： A single-ended sense amplifier and a memory device including the same are presented. A sense amplifier, which senses and amplifies data of a memory cell, may include a precharge circuit pre-charging a data line which is connected to the memory cell and provides a sensing voltage, and a reference line which provides a reference voltage, with a power supply voltage; a reference voltage generating circuit which generates the reference voltage by discharging the reference line based on a reference current, and adjusts an amount of the reference current based on the data of the memory cell; and a comparator which compares the sensing voltage and the reference voltage, and outputs a comparison result as the data of the memory cell.

公开(公告)号：US20170316833A1

公开(公告)日：2017-11-02

申请号：US15452885

申请日：2017-03-08

申请人： Jeong-don IHM ,  Siddharth KATARE ,  Hyun-jin KIM

发明人： Jeong-don IHM ,  Siddharth KATARE ,  Hyun-jin KIM

IPC分类号： G11C16/28 ,  H01L27/11573 ,  G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11582 ,  H01L27/11568

CPC分类号： G11C16/28 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C16/0483 ,  G11C16/24 ,  H01L27/11582

摘要： A single-ended sense amplifier and a memory device including the same are presented. A sense amplifier, which senses and amplifies data of a memory cell, may include a precharge circuit pre-charging a data line which is connected to the memory cell and provides a sensing voltage, and a reference line which provides a reference voltage, with a power supply voltage; a reference voltage generating circuit which generates the reference voltage by discharging the reference line based on a reference current, and adjusts an amount of the reference current based on the data of the memory cell; and a comparator which compares the sensing voltage and the reference voltage, and outputs a comparison result as the data of the memory cell.

公开(公告)号：US06232811B1

公开(公告)日：2001-05-15

申请号：US09476212

申请日：1999-12-30

申请人： Jeong Don Ihm

发明人： Jeong Don Ihm

IPC分类号： H03H1126

CPC分类号： H03L7/00 ,  G06F1/10

摘要： There is provided a circuit for controlling the setup/hold time of a semiconductor device, including: a setup/hold on signal generator for generating a setup/hold on signal of the semiconductor device; a comparison signal generator for converting the difference between pulse widths of the setup on signal and hold on signal of the setup/hold on signal generator into the voltage difference across an inner capacitor, to generate a comparison signal for the setup/hold time; a comparison signal detector for detecting the comparison signal generated by the comparison signal generator and amplifying it to a predetermined level; a clock delay path selection signal generator for generating a clock delay path selection signal according to the level of the signal detected by the comparison signal detector; and a clock/command signal processor for outputting a clock signal and command signal applied to input pads as an inner clock signal and inner command signal whose delays are compensated according to the clock delay path selection signal, to thereby sufficiently secure the margin of the setup/hold time.

摘要翻译： 提供了一种用于控制半导体器件的建立/保持时间的电路，包括：用于产生半导体器件的建立/保持信号的信号发生器的建立/保持; 比较信号发生器，用于将建立开启信号的脉冲宽度和信号发生器上的建立/保持信号的保持信号之间的差异转换成内部电容器两端的电压差，以产生建立/保持时间的比较信号; 比较信号检测器，用于检测由比较信号发生器产生的比较信号并将其放大到预定电平; 时钟延迟路径选择信号发生器，用于根据比较信号检测器检测到的信号的电平产生时钟延迟路径选择信号; 以及时钟/命令信号处理器，用于输出施加到输入焊盘的时钟信号和指令信号作为内部时钟信号，并且根据时钟延迟路径选择信号补偿其延迟的内部指令信号，从而充分确保设置的余量 /保持时间。