公开(公告)号：US5850509A

公开(公告)日：1998-12-15

申请号：US778182

申请日：1997-01-02

申请人： Mickey L. Fandrich ,  Jerry A. Kreifels ,  Virgil N. Kynett

发明人： Mickey L. Fandrich ,  Jerry A. Kreifels ,  Virgil N. Kynett

IPC分类号： G11C29/12 ,  G11C29/14 ,  G06F11/00 ,  G11C29/00

CPC分类号： G11C29/12 ,  G11C29/14

摘要： Circuitry for propagating test mode signals associated with a memory array including a plurality of circuits for storing test mode signals, apparatus for selectively providing test mode data to each of the circuits for storing test mode signals, and apparatus for simultaneously activating all of the circuits for storing test mode signals to provide output signals to be used for testing.

摘要翻译： 用于传播与包括用于存储测试模式信号的多个电路的存储器阵列相关联的测试模式信号的电路，用于选择性地向每个用于存储测试模式信号的电路提供测试模式数据的设备，以及用于同时激活所有电路的设备 存储测试模式信号以提供要用于测试的输出信号。

公开(公告)号：US5410544A

公开(公告)日：1995-04-25

申请号：US085641

申请日：1993-06-30

申请人： Jerry A. Kreifels ,  Mamun Rashid ,  Rodney R. Rozman ,  Richard J. Durante

发明人： Jerry A. Kreifels ,  Mamun Rashid ,  Rodney R. Rozman ,  Richard J. Durante

IPC分类号： G11C29/48 ,  G06F11/00

CPC分类号： G11C29/48

摘要： An apparatus for testing a unit comprising an internal processor coupled to a register by an internal bus. The internal processor is programmed so that it can execute an algorithm. When executed, the algorithm performs an operation on the unit. The register is for storing a state datum. The internal bus is used by the internal processor to access the state datum when the internal processor is executing the algorithm. The testing apparatus comprises an external processor disposed external to the unit and an interface and switch disposed on the unit. The interface is coupled to the internal and external processors and is for receiving a plurality of commands from the external processor. The commands include an internal processor command and an open trap command. If issued, the internal processor command causes the internal processor to execute the algorithm. The switch is coupled to the interface and coupled between the internal processor and the internal bus. If the interface receives the open trap command, the switch permits the external processor to access the state datum of the register.

摘要翻译： 一种用于测试单元的装置，包括通过内部总线耦合到寄存器的内部处理器。 内部处理器被编程为可以执行一个算法。 执行时，算法对单元执行操作。 寄存器用于存储状态数据。 当内部处理器执行算法时，内部总线由内部处理器使用来访问状态数据。 测试装置包括设置在该单元外部的外部处理器和设置在该单元上的接口和开关。 该接口耦合到内部和外部处理器，并用于从外部处理器接收多个命令。 这些命令包括内部处理器命令和打开的陷阱命令。 如果发出内部处理器命令，内部处理器将执行该算法。 该开关耦合到接口并耦合在内部处理器和内部总线之间。 如果接口接收到打开的trap命令，则交换机允许外部处理器访问寄存器的状态数据。

公开(公告)号：US5053990A

公开(公告)日：1991-10-01

申请号：US157361

申请日：1988-02-17

申请人： Jerry A. Kreifels ,  Alan Baker ,  George Hoekstra ,  Virgil N. Kynett ,  Steven Wells ,  Mark Winston

发明人： Jerry A. Kreifels ,  Alan Baker ,  George Hoekstra ,  Virgil N. Kynett ,  Steven Wells ,  Mark Winston

IPC分类号： G11C17/00 ,  G06F12/00 ,  G11C16/02 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34 ,  G11C29/00 ,  G11C29/14

CPC分类号： G11C16/3445 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/3459

摘要： A semiconductor flash EPROM/EEPROM device which includes a command port for receiving instruction on a data line and providing control signals to a memory for providing program and erase functions, a method to program and erase the memory. A program sequence is comprised of setting up a program command during a first write cycle, preforming a second write cycle to load address to address register and data to to a data register, programming during a program cycle and writing a program verify command during a third write cycle to verify the programmed data during a read cycle. An erase sequence is comprised of writing a setup erase command during a first write cycle, an erase command during a second write cycle providing the erasure during an erase cycle, writing the erase verify command during a third write cycle which also addresses the address of the memory and providing erase verification during a read cycle. Both the erase and program cycles provide for measured incremental erasing and programming.

摘要翻译： 一种半导体闪存EPROM / EEPROM器件，包括用于在数据线上接收指令并向存储器提供控制信号以提供编程和擦除功能的命令端口，编程和擦除存储器的方法。 程序序列包括在第一写周期期间设置程序命令，执行第二写周期以将地址寄存器加载到地址寄存器和数据到数据寄存器，在程序周期期间进行编程以及在第三写入期间写入程序验证命令 写周期以在读周期中验证编程数据。 擦除序列包括在第一写周期期间写入建立擦除命令，在擦除周期期间提供擦除的第二写周期期间的擦除命令，在第三写周期期间写入擦除验证命令，该第三写周期还解决 存储器并在读周期期间提供擦除验证。 擦除和编程周期都提供测量的增量擦除和编程。

公开(公告)号：US5339320A

公开(公告)日：1994-08-16

申请号：US791772

申请日：1991-11-12

申请人： Mickey L. Fandrich ,  Jerry A. Kreifels ,  Virgil N. Kynett

发明人： Mickey L. Fandrich ,  Jerry A. Kreifels ,  Virgil N. Kynett

IPC分类号： G01R31/317 ,  G01R31/28

CPC分类号： G01R31/31701

摘要： An arrangement for generating signals for generating a particular set of test conditions within a digital circuit including a plurality of latches for storing individual bits of data representing individual operations to be accomplished within the digital circuitry, the latches each having input and output terminals; the output terminals of each of the latches being connected to individual portions of the digital circuitry to effect an individual operation thereby; apparatus connected to the input terminals of the latches for setting individual selected ones of the latches to provide selected test conditions; and apparatus for transferring the condition of a selected number of the latches simultaneously to effect a selected test condition.

摘要翻译： 一种用于产生信号的装置，用于在数字电路内生成特定的一组测试条件，包括多个锁存器，用于存储表示在数字电路内完成的各个操作的各个数据位，每个具有输入和输出端子的锁存器; 每个锁存器的输出端子连接到数字电路的各个部分，从而实现单独的操作; 连接到所述锁存器的输入端子的装置，用于设置所述锁存器中的所选择的一个，以提供所选择的测试条件; 以及用于同时转移选定数量的锁存器的状态以实现所选择的测试条件的装置。

公开(公告)号：US07437499B2

公开(公告)日：2008-10-14

申请号：US11322918

申请日：2005-12-30

申请人： Richard J. Durante ,  Jerry A. Kreifels

发明人： Richard J. Durante ,  Jerry A. Kreifels

IPC分类号： G06F12/00

CPC分类号： G11C16/20 ,  G11C16/10 ,  G11C16/32

摘要： A flash memory that could not have completed an operation within a time required by a host may be able to work with the host by dividing the operation into phases that may be completed within the allocated time. As a result, a type of memory that would otherwise be unable to be implemented in a format, such as a memory card, may be used effectively.

摘要翻译： 在主机所需的时间内无法完成操作的闪存可以通过将操作分成在分配的时间内可以完成的阶段来与主机一起工作。 结果，可以有效地使用否则将不能以诸如存储卡的格式实现的存储器的类型。

公开(公告)号：US07200708B1

公开(公告)日：2007-04-03

申请号：US10750364

申请日：2003-12-31

申请人： Jerry A. Kreifels

发明人： Jerry A. Kreifels

IPC分类号： G11C16/02

CPC分类号： G11C16/16 ,  G11C16/349 ,  G11C2029/4402

摘要： In some embodiments, an apparatus and methods for storing data which self-compensate for erase performance degradation. Such an apparatus includes, in an exemplary embodiment, a plurality of memory blocks individually erasable during erase cycles by the application of erase pulses thereto having appropriate erase pulse voltage levels, and a memory location uniquely associated with each memory block that stores an initial erase pulse voltage level therefor to be used during an erase cycle. Such methods include, in an exemplary embodiment, counting the number of erase pulses applied to each memory block during an erase cycle therefor, comparing the count for each memory block to a threshold count value, and updating the stored initial erase pulse voltage level to be used during a subsequent erase cycle for each respective memory block if the count for that memory block is not less than the threshold count. Other embodiments are described and claimed.

摘要翻译： 在一些实施例中，一种用于存储自我补偿擦除性能降低的数据的装置和方法。 在示例性实施例中，这样的装置包括在擦除周期期间通过施加具有适当的擦除脉冲电压电平的擦除脉冲而可擦除的多个存储器块，以及与存储初始擦除脉冲的每个存储块唯一相关联的存储单元 在擦除周期期间使用其电压电平。 在示例性实施例中，这样的方法包括在擦除周期期间对施加到每个存储器块的擦除脉冲数进行计数，将每个存储块的计数与阈值计数值进行比较，并将存储的初始擦除脉冲电压电平更新为 如果该存储器块的计数不小于阈值计数，则在每个相应存储器块的后续擦除周期期间使用。 描述和要求保护其他实施例。

公开(公告)号：US06597605B2

公开(公告)日：2003-07-22

申请号：US10139057

申请日：2002-05-03

申请人： Jerry A. Kreifels ,  Rodney R. Rozman

发明人： Jerry A. Kreifels ,  Rodney R. Rozman

IPC分类号： G11C700

CPC分类号： G11C16/10 ,  G11C16/3454

摘要： Systems including a bit sequence program controller to program in sequence non-volatile memory cells in an array of programmable non-volatile memory cells. The bit sequence program controller determines the bits that require programming by comparing the bits of the program word with an erased logical state of the array of programmable non-volatile memory cells. The bit sequence program controller further indicates which non-volatile memory cells in a word of non-volatile memory cells in the array of non-volatile memory cells require programming to match the program word. The bit sequence program controller counts the number of the bits that require programming in the program word by counting the number of bits of the program word that are not in an erased logical state to determine when the programming should be completed.

摘要翻译： 包括位序列程序控制器的系统，用于在可编程非易失性存储器单元阵列中对序列中的非易失性存储单元进行编程。 比特序列程序控制器通过将程序字的位与可编程非易失性存储单元的阵列的擦除逻辑状态进行比较来确定需要编程的位。 比特序列程序控制器进一步指示非易失性存储器单元阵列中的非易失性存储单元的单词中的哪些非易失性存储单元需要编程以匹配程序字。 比特序列程序控制器通过对不在擦除逻辑状态的程序字的位数进行计数来确定程序字中编程的位数，来确定编程应该何时完成。

公开(公告)号：US06418059B1

公开(公告)日：2002-07-09

申请号：US09603671

申请日：2000-06-26

申请人： Jerry A. Kreifels ,  Rodney R. Rozman

发明人： Jerry A. Kreifels ,  Rodney R. Rozman

IPC分类号： G11C700

CPC分类号： G11C16/10 ,  G11C16/3454

摘要： A bit sequence program controller to program in sequence non-volatile memory cells in an array of programmable non-volatile memory cells. The bit sequence program controller determines the bits that require programming by comparing the bits of the program word with an erased logical state of the array of programmable non-volatile memory cells. The bit sequence program controller further indicates which non-volatile memory cells in a word of non-volatile memory cells in the array of non-volatile memory cells require programming to match the program word. The bit sequence program controller counts the number of the bits that require programming in the program word by counting the number of bits of the program word that are not in an erased logical state to determine when the programming should be completed.

摘要翻译： 一种位序列程序控制器，用于对可编程非易失性存储单元阵列中的非易失性存储器单元进行编程。 比特序列程序控制器通过将程序字的位与可编程非易失性存储单元的阵列的擦除逻辑状态进行比较来确定需要编程的位。 比特序列程序控制器进一步指示非易失性存储器单元阵列中的非易失性存储单元的单词中的哪些非易失性存储单元需要编程以匹配程序字。 比特序列程序控制器通过对不在擦除逻辑状态的程序字的位数进行计数来确定程序字中编程的位数来确定编程应该何时完成，从而对需要编程的位数进行计数。

公开(公告)号：US5526311A

公开(公告)日：1996-06-11

申请号：US175599

申请日：1993-12-30

申请人： Jerry A. Kreifels ,  Richard J. Durante ,  Alexander C. Mitchell, III

发明人： Jerry A. Kreifels ,  Richard J. Durante ,  Alexander C. Mitchell, III

IPC分类号： G01R31/317 ,  G11C29/46 ,  G11C29/00

CPC分类号： G01R31/31701 ,  G11C29/46

摘要： A method of enabling access to a test mode of a semiconductor memory in response to user commands. The method enables test mode access only when a number of "keys" are presented in the proper sequence via the memory device pins. During the first phase of the unlocking process, an array controller determines whether the correct confirmation codes were input via the address and data pins. If they were, the array controller proceeds to the second phase of the unlocking process. During the second phase voltage levels on selected control pins are checked for a transition to a first voltage level. If the control pins transition as required, the array controller proceeds to the third phase. During the third phase, the array controller waits a limited time for receipt of a second test mode enable command. The second test mode enable command must be followed by correct confirmation codes. If the third phase is successfully completed, the array controller writes to a test mode enable access register. As a result, an enable test mode signal becomes active, which allows the user interlace to respond to subsequently issued test mode commands. Also described is a method of eliminating access to the test mode of the semiconductor memory device, which includes a nonvolatile instruction memory.

摘要翻译： 一种能够响应于用户命令访问半导体存储器的测试模式的方法。 该方法仅在通过存储器件引脚以适当顺序呈现多个“键”时才允许测试模式访问。 在解锁过程的第一阶段，阵列控制器确定是否通过地址和数据引脚输入了正确的确认码。 如果是，阵列控制器进入解锁过程的第二阶段。 在第二阶段期间，检查所选择的控制引脚上的电压电平以转换到第一电压电平。 如果控制引脚根据需要进行转换，则阵列控制器进入第三阶段。 在第三阶段期间，阵列控制器等待有限的时间接收第二测试模式使能命令。 第二个测试模式使能命令必须遵循正确的确认代码。 如果第三阶段成功完成，阵列控制器写入测试模式使能访问寄存器。 因此，使能测试模式信号变为有效，这允许用户交织响应随后发出的测试模式命令。 还描述了一种消除对包括非易失性指令存储器的半导体存储器件的测试模式的访问的方法。

公开(公告)号：US4841482A

公开(公告)日：1989-06-20

申请号：US157364

申请日：1988-02-17

申请人： Jerry A. Kreifels ,  George Hoekstra

发明人： Jerry A. Kreifels ,  George Hoekstra

IPC分类号： G11C16/34 ,  G11C29/02 ,  G11C29/50

CPC分类号： G11C16/345 ,  G11C16/344 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50 ,  G11C16/04 ,  G11C2029/5006

摘要： A circuit and method for verifying leakage in a flash EPROM/EEPROM memory cell which is fabricated on a silicon substrate having floating gate. A word line coupled to the control gate of the memory cell is typically at ground potential, but during a test mode a positive voltage is placed on the control gate and leakage current at the drain is measured. A good cell will typically have zero or negligible drain leakage current, however, a cell which is susceptible to being overerased will exhibit appreciable leakage current. A circuit is implemented on the chip with the memory for switching a positive voltage onto the word line during the test mode.

摘要翻译： 一种用于验证在具有浮动栅极的硅衬底上制造的闪存EPROM / EEPROM存储单元中的泄漏的电路和方法。 耦合到存储单元的控制栅极的字线通常处于地电位，但是在测试模式期间，在控制栅极上放置正电压，并测量漏极处的漏电流。 良好的电池通常具有零或可忽略的漏极漏电流，然而，容易被过度烧蚀的电池将会呈现明显的漏电流。 在芯片上实现一个电路，用于在测试模式期间将正电压切换到字线上的存储器。