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公开(公告)号：US5053990A
公开(公告)日：1991-10-01
申请号：US157361
申请日：1988-02-17
申请人： Jerry A. Kreifels , Alan Baker , George Hoekstra , Virgil N. Kynett , Steven Wells , Mark Winston
发明人： Jerry A. Kreifels , Alan Baker , George Hoekstra , Virgil N. Kynett , Steven Wells , Mark Winston
IPC分类号： G11C17/00 , G06F12/00 , G11C16/02 , G11C16/10 , G11C16/16 , G11C16/34 , G11C29/00 , G11C29/14
CPC分类号： G11C16/3445 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/3459
摘要： A semiconductor flash EPROM/EEPROM device which includes a command port for receiving instruction on a data line and providing control signals to a memory for providing program and erase functions, a method to program and erase the memory. A program sequence is comprised of setting up a program command during a first write cycle, preforming a second write cycle to load address to address register and data to to a data register, programming during a program cycle and writing a program verify command during a third write cycle to verify the programmed data during a read cycle. An erase sequence is comprised of writing a setup erase command during a first write cycle, an erase command during a second write cycle providing the erasure during an erase cycle, writing the erase verify command during a third write cycle which also addresses the address of the memory and providing erase verification during a read cycle. Both the erase and program cycles provide for measured incremental erasing and programming.
摘要翻译： 一种半导体闪存EPROM / EEPROM器件，包括用于在数据线上接收指令并向存储器提供控制信号以提供编程和擦除功能的命令端口，编程和擦除存储器的方法。 程序序列包括在第一写周期期间设置程序命令，执行第二写周期以将地址寄存器加载到地址寄存器和数据到数据寄存器，在程序周期期间进行编程以及在第三写入期间写入程序验证命令 写周期以在读周期中验证编程数据。 擦除序列包括在第一写周期期间写入建立擦除命令，在擦除周期期间提供擦除的第二写周期期间的擦除命令，在第三写周期期间写入擦除验证命令，该第三写周期还解决 存储器并在读周期期间提供擦除验证。 擦除和编程周期都提供测量的增量擦除和编程。
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公开(公告)号：US5222046A
公开(公告)日：1993-06-22
申请号：US601012
申请日：1990-10-19
申请人： Jerry A. Kreifels , Alan Baker , George Hoekstra , Virgil N. Kynett , Steven Wells , Mark Winston
发明人： Jerry A. Kreifels , Alan Baker , George Hoekstra , Virgil N. Kynett , Steven Wells , Mark Winston
摘要： A semiconductor flash EPROM/EEPROM device which includes a command port controller for receiving command instructions from a data bus coupled to the memory device. Instruction words to a command port controller operates to instruct the device to perform read, erase, program, or verify functions and the command port controller generates necessary control signals to cause the memory to function appropriately. By utilizing the command port controller the memory device can be erased and programmed while the device is in the circuit and permits pin compatibility with the prior art EPROM and EEPROMs.
摘要翻译： 一种半导体闪存EPROM / EEPROM器件，其包括命令端口控制器，用于从耦合到存储器件的数据总线接收命令指令。 命令端口控制器的指令字用于指示设备执行读取，擦除，编程或验证功能，并且命令端口控制器产生必要的控制信号以使存储器正常工作。 通过利用命令端口控制器，存储器件可以在器件在电路中被擦除和编程，并允许引脚与现有技术的EPROM和EEPROM兼容。
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3.发明授权Circuitry for propagating test mode signals associated with a memory array 失效用于传播与存储器阵列相关联的测试模式信号的电路
公开(公告)号：US5850509A
公开(公告)日：1998-12-15
申请号：US778182
申请日：1997-01-02
摘要： Circuitry for propagating test mode signals associated with a memory array including a plurality of circuits for storing test mode signals, apparatus for selectively providing test mode data to each of the circuits for storing test mode signals, and apparatus for simultaneously activating all of the circuits for storing test mode signals to provide output signals to be used for testing.
摘要翻译： 用于传播与包括用于存储测试模式信号的多个电路的存储器阵列相关联的测试模式信号的电路，用于选择性地向每个用于存储测试模式信号的电路提供测试模式数据的设备，以及用于同时激活所有电路的设备 存储测试模式信号以提供要用于测试的输出信号。
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公开(公告)号：US5339320A
公开(公告)日：1994-08-16
申请号：US791772
申请日：1991-11-12
IPC分类号： G01R31/317 , G01R31/28
CPC分类号： G01R31/31701
摘要： An arrangement for generating signals for generating a particular set of test conditions within a digital circuit including a plurality of latches for storing individual bits of data representing individual operations to be accomplished within the digital circuitry, the latches each having input and output terminals; the output terminals of each of the latches being connected to individual portions of the digital circuitry to effect an individual operation thereby; apparatus connected to the input terminals of the latches for setting individual selected ones of the latches to provide selected test conditions; and apparatus for transferring the condition of a selected number of the latches simultaneously to effect a selected test condition.
摘要翻译： 一种用于产生信号的装置，用于在数字电路内生成特定的一组测试条件，包括多个锁存器，用于存储表示在数字电路内完成的各个操作的各个数据位，每个具有输入和输出端子的锁存器; 每个锁存器的输出端子连接到数字电路的各个部分，从而实现单独的操作; 连接到所述锁存器的输入端子的装置，用于设置所述锁存器中的所选择的一个，以提供所选择的测试条件; 以及用于同时转移选定数量的锁存器的状态以实现所选择的测试条件的装置。
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5.发明授权
公开(公告)号：US5341330A
公开(公告)日：1994-08-23
申请号：US145732
申请日：1993-11-01
申请人： Steven E. Wells , Mark Winston , Virgil N. Kynett
发明人： Steven E. Wells , Mark Winston , Virgil N. Kynett
CPC分类号： G06F3/0601 , G11C16/102 , G06F2003/0694 , G06F2212/2022
摘要： A method for writing data to an entry in a portion of a flash EEPROM memory array during a period in which that portion of the array is being erased and writing is prohibited. The method includes writing the data to a new entry position apart from the portion of the array which is being erased along with a revision number which is greater than the revision number of the original data in the original portion of the array, writing of the busy condition of the original entry to a temporary storage position apart from the portion of the array which is being erased, and invalidating entries listed in the temporary storage position when the erase operation is concluded.
摘要翻译： 在数据的该部分被擦除和写入的时段期间，将数据写入快闪EEPROM存储器阵列的一部分中的条目的方法被禁止。 该方法包括将数据写入除了正被擦除的阵列的部分之外的新的入口位置以及比阵列的原始部分中的原始数据的修订版本号大的修订版本号，写入忙 原始条目到除了被擦除的阵列的部分之外的临时存储位置的条件，以及当擦除操作结束时使临时存储位置中列出的条目无效。
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6.发明授权Nonvolatile memory with blocks and circuitry for selectively protecting the blocks for memory operations 失效具有用于选择性地保护块以用于存储器操作的块和电路的非易失性存储器
公开(公告)号：US5513136A
公开(公告)日：1996-04-30
申请号：US358978
申请日：1994-12-19
摘要： A nonvolatile memory comprises a memory array and a control circuit coupled to the memory array for performing memory operations with respect to the memory array. A storage circuit associated with the memory array is provided for storing a data. When the data is stored in the storage circuit, the memory array is locked from being accessed for the memory operations. A logic circuit is coupled to the control circuit and the storage circuit for preventing the control circuit from accessing the memory array with respect to the memory operations in accordance with the data. The logic circuit prevents the control circuit from accessing the memory array when the storage circuit stores the data. A control input is provided for receiving a control signal. The control signal is applied to the logic circuit and can be in a first voltage state and a second voltage state. When the control signal is in the first voltage state, the logic circuit is enabled to lock the memory array with respect to the memory operations in accordance with the data stored in the storage circuit. When the control signal is in the second voltage state, the logic circuit is disabled to lock the memory array and the memory array is allowed for the memory operations regardless of the data stored in the storage circuit.
摘要翻译： 非易失性存储器包括存储器阵列和耦合到存储器阵列的控制电路，用于执行存储器阵列的存储器操作。 提供与存储器阵列相关联的存储电路用于存储数据。 当数据存储在存储电路中时，存储器阵列被锁定以进行存储器操作。 逻辑电路耦合到控制电路和存储电路，用于根据数据防止控制电路相对于存储器操作访问存储器阵列。 当存储电路存储数据时，逻辑电路防止控制电路访问存储器阵列。 提供控制输入用于接收控制信号。 控制信号被施加到逻辑电路并且可以处于第一电压状态和第二电压状态。 当控制信号处于第一电压状态时，逻辑电路能够根据存储在存储电路中的数据相对于存储器操作锁定存储器阵列。 当控制信号处于第二电压状态时，无论存储在存储电路中的数据如何，逻辑电路被禁用以锁定存储器阵列，并且存储器阵列被允许用于存储器操作。
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7.发明授权Circuitry and method for programming and erasing a non-volatile semiconductor memory 失效用于编程和擦除非易失性半导体存储器的电路和方法
公开(公告)号：US5448712A
公开(公告)日：1995-09-05
申请号：US201044
申请日：1994-02-24
CPC分类号： G11C16/3445 , G11C16/102 , G11C16/3436 , G11C16/3459
摘要： Erase control circuitry for erasing a flash memory array. The erase control circuitry resides on the same substrate as the flash memory array, along with a command state machine. The command state machine recognizes and externally generated erase command applied to the terminals and generates an active erase control signal, to which the erase control circuitry responds. The erase control circuitry includes precondition pulse application circuitry, erase pulse application circuitry and erase verification circuitry. The precondition pulse application circuitry preconditions the array by programming each bit in the flash memory to a threshold voltage level representative of a programmed state. The erase pulse application circuitry applies a single erase pulse at a time to the flash memory array to erase the flash array by bringing the threshold voltage level of each cell in the array to a level representative of an erased state. The erase verification circuitry verifies the erasure of the flash memory array on a byte by byte basis. If the byte currently being verified has been erased; the erase verification circuitry brings a match signal to an active level. The erase control circuitry determines whether additional erase pulses should be applied to the flash array based upon the match signal and the number of erase pulses previously applied to the flash array described is program control circuitry and methods of programming and erasing a flash memory array in response to two step command sequences.
摘要翻译： 擦除控制电路以擦除闪存阵列。 擦除控制电路与命令状态机一起位于与闪存阵列相同的衬底上。 命令状态机识别并向外部产生的擦除命令，并产生一个有效的擦除控制信号，擦除控制电路对其进行响应。 擦除控制电路包括预处理脉冲应用电路，擦除脉冲应用电路和擦除验证电路。 预处理脉冲应用电路通过将闪速存储器中的每个位编程为表示编程状态的阈值电压电平来预先调整阵列。 擦除脉冲施加电路通过将阵列中的每个单元的阈值电压电平提升到表示擦除状态的电平，将一次擦除脉冲一次施加到闪存阵列以擦除闪存阵列。 擦除验证电路以逐个字节为基础来验证闪速存储器阵列的擦除。 如果当前正在验证的字节已被擦除; 擦除验证电路将匹配信号带到活动电平。 擦除控制电路基于匹配信号确定是否应该向闪存阵列施加额外的擦除脉冲，并且先前施加到所述闪存阵列的擦除脉冲的数量是程序控制电路以及响应于编程和擦除闪存阵列的方法 到两步命令序列。
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8.发明授权Apparatus for determining the conditions of programming circuitry used with flash EEPROM memory 失效用于确定与闪存EEPROM存储器一起使用的编程电路条件的装置
公开(公告)号：US5224070A
公开(公告)日：1993-06-29
申请号：US804965
申请日：1991-12-11
IPC分类号： G11C17/00 , G11C16/02 , G11C16/10 , G11C16/34 , G11C29/44 , G11C29/52 , H01L21/822 , H01L27/04
CPC分类号： G11C16/10 , G11C16/3436 , G11C29/44 , G11C29/52 , G11C2216/20
摘要： A circuit which monitors the internal state of flash memory array programming circuitry and conveys that state to circuitry external to the flash memory array so that external circuitry need not delay during any period in which a programming operation is taking place within the flash memory array.
摘要翻译： 监视闪存阵列编程电路的内部状态并将该状态传送到闪速存储器阵列外部的电路的电路，使得外部电路不需要在闪存阵列内发生编程操作的任何周期期间延迟。
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9.发明授权
公开(公告)号：US5197034A
公开(公告)日：1993-03-23
申请号：US773247
申请日：1991-10-09
摘要： A non-volatile memory is described. The memory includes a memory array that includes a main block and a boot block. The memory also includes a control input for receiving a control signal. The control signal can be in a first voltage state, a second voltage state, and a third voltage state. Circuitry means is coupled to receive the control signal at the control input for (1) allowing the boot block to be updated when the control signal is in the first state and for (2) generating a power off signal to switch the memory into a substantially powered off state when the control signal is in the third voltage state. A method of controlling a non-volatile memory is also described.
摘要翻译： 描述非易失性存储器。 存储器包括包括主块和引导块的存储器阵列。 存储器还包括用于接收控制信号的控制输入。 控制信号可以处于第一电压状态，第二电压状态和第三电压状态。 电路装置被耦合以在控制输入处接收控制信号，用于（1）当控制信号处于第一状态时允许引导块被更新，并且（2）产生电源关闭信号以将存储器切换到基本上 当控制信号处于第三电压状态时，断电状态。 还描述了一种控制非易失性存储器的方法。
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公开(公告)号：US5463757A
公开(公告)日：1995-10-31
申请号：US185449
申请日：1994-01-21
CPC分类号： G11C16/32 , G11C16/10 , G11C2216/20
摘要： A command state machine for control circuitry associated with a memory array which control circuitry includes apparatus for programming and erasing the memory array including first state machine logic apparatus for providing control signals for reading the memory array and for initiating operations of the apparatus for programming and erasing the memory array in response to commands, and second state machine logic apparatus for controlling information derived from the memory array, the first and second state machine logic apparatus being adapted to assume predetermined states in response to any invalid command which have no adverse affect on the memory array or the control circuitry.
摘要翻译： 一种用于与存储器阵列相关联的控制电路的命令状态机，所述控制电路包括用于编程和擦除存储器阵列的装置，所述装置包括用于提供用于读取存储器阵列的控制信号的第一状态机逻辑装置，以及用于启动用于编程和擦除的装置的操作 所述存储器阵列响应于命令，以及用于控制从所述存储器阵列导出的信息的第二状态机逻辑装置，所述第一和第二状态机逻辑装置适于响应于对所述存储阵列没有不利影响的任何无效命令而呈现预定状态 存储器阵列或控制电路。
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