利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

245 条记录 (耗时 0.028 秒)

    TIMING DETERMINATION-TYPE GAMING DEVICE AND METHOD
    1.
    发明申请
    TIMING DETERMINATION-TYPE GAMING DEVICE AND METHOD 审中-公开

    公开(公告)号：US20180311580A1

    公开(公告)日：2018-11-01

    申请号：US15770180

    申请日：2016-12-07

    申请人： Jin Young KIM

    发明人： Jin Young KIM

    IPC分类号： A63F13/44 ,  A63F13/814

    CPC分类号： A63F13/44 ,  A63F13/2145 ,  A63F13/52 ,  A63F13/814

    摘要： Disclosed are a timing determination-type game apparatus and method. The present invention may provide a new type of timing determination-type game in which a user operates at least one timing pointer or at least one input pointer to match each other at the same position at a designated timing while moving at least one timing pointer or at least one input pointer in the unit of a group regardless of a path. Further, according to the present invention, it is possible to simultaneously move a plurality of timing pointers or a plurality of input pointers in the unit of the group without damaging timing information provided by the timing pointer and the input pointer, thereby providing various user interfaces for operating the game.

    Wireless network connection controlling method using device impact, application program controlling method, and devices thereof
    2.
    发明授权
    Wireless network connection controlling method using device impact, application program controlling method, and devices thereof 有权
    使用设备影响的无线网络连接控制方法，应用程序控制方法及其装置

    公开(公告)号：US09313314B2

    公开(公告)日：2016-04-12

    申请号：US13265559

    申请日：2010-03-23

    申请人： Jin Young Kim ,  Jin Yeop Chang ,  Hyo Jin Yoon ,  Won-Il Lee ,  Chung Hyeok Lee

    发明人： Jin Young Kim ,  Jin Yeop Chang ,  Hyo Jin Yoon ,  Won-Il Lee ,  Chung Hyeok Lee

    IPC分类号： H04L12/28 ,  H04M1/725 ,  G06F1/16 ,  H04Q1/00 ,  H04L12/24

    CPC分类号： H04M1/7253 ,  G06F1/1694 ,  G06F2200/1636 ,  H04L41/04 ,  H04L41/12 ,  H04M2250/12 ,  H04Q1/00

    摘要： Wireless network connection control method of performing control for establishing and releasing wireless network connection with another device when impacts are applied to devices, application program control method of performing control for setting and executing application program when impacts are applied to devices, and device including wireless network connection control function and application program control function which use a device impact are disclosed. According to the present invention, provided is a wireless network connection control method of a device using a device impact, including generating a corresponding impact event when physical impact applied from the outside is sensed, transceiving a search message between devices based on a time at which the impact event occurred, searching for another device in which the impact event has occurred at the same time, and performing a predetermined protocol with a corresponding device according to a search result and establishing an inter-device wireless network connection.

    摘要翻译： 无线网络连接控制方法，当对设备施加影响时，执行用于建立和释放与另一设备的无线网络连接的控制，当对设备施加影响时执行用于设置和执行应用程序的控制的应用程序控制方法，以及包括无线网络 公开了使用设备影响的连接控制功能和应用程序控制功能。 根据本发明，提供了一种使用设备影响的设备的无线网络连接控制方法，包括当感测到从外部施加的物理冲击时产生相应的冲击事件，在设备之间基于时间来收发搜索消息 发生影响事件，同时搜索影响事件发生的其他设备，并根据搜索结果与对应的设备执行预定协议，并建立设备间无线网络连接。

    Functional Pillow for Preventing Head Deformation of Infants Due to Posture
    4.
    发明申请
    Functional Pillow for Preventing Head Deformation of Infants Due to Posture 审中-公开
    功能枕头防止由于姿势引起的婴儿头部变形

    公开(公告)号：US20130305458A1

    公开(公告)日：2013-11-21

    申请号：US13982998

    申请日：2011-06-08

    申请人： Jin young Kim

    发明人： Jin young Kim

    IPC分类号： A47G9/10

    CPC分类号： A47G9/10 ,  A61F5/05891 ,  A61G7/05715 ,  A61G13/121

    摘要： The present invention relates to a functional pillow for preventing positional head deformity of an infant. The functional pillow includes an inner foam member which is porous, an outer cover which encloses the inner foam member and includes a plurality of through-holes formed thereon, a head seating portion which is formed on at least one of a top surface and a bottom surface of a pillow body which includes the inner foam member and the outer cover in an eccentric position to allow a head to be placed thereon, and at least one layered auxiliary pillow which is inserted into the head seating portion and includes an auxiliary head seating portion of a different size formed on a surface. A degree of layering of the auxiliary pillow is different according to a head size.

    摘要翻译： 本发明涉及一种用于防止婴儿的位置头畸形的功能性枕头。 所述功能性枕头包括多孔的内部泡沫构件，封闭所述内部泡沫构件并且包括形成在其上的多个通孔的外盖，头部座部，其形成在顶部表面和底部的至少一个上 枕头主体的表面，其包括内部泡沫构件和外盖，偏心位置以允许头部放置在其上;以及至少一个分层的辅助枕头，其插入到头部支座部分中，并且包括辅助头部支座部分 形成在表面上的不同尺寸。 辅助枕头的层次程度根据头部大小而不同。

    Flash memory devices with selective bit line discharge paths and methods of operating the same
    7.
    发明授权
    Flash memory devices with selective bit line discharge paths and methods of operating the same 有权
    具有选择性位线放电路径的闪存器件及其操作方法

    公开(公告)号：US08363482B2

    公开(公告)日：2013-01-29

    申请号：US12813050

    申请日：2010-06-10

    申请人： Euido Kim ,  BongYong Lee ,  Haebum Lee ,  Sang-Youl Kwon ,  Jin-Young Kim ,  Hye Yeon Yun ,  Houng-kuk Jang

    发明人： Euido Kim ,  BongYong Lee ,  Haebum Lee ,  Sang-Youl Kwon ,  Jin-Young Kim ,  Hye Yeon Yun ,  Houng-kuk Jang

    IPC分类号： G11C11/34

    CPC分类号： G11C16/06

    摘要： Provided is a flash memory device that can include a memory cell configured to store data, a local bit line that is connected to the memory cell, a global bit line that is connected to the local bit line, a discharge transistor that is connected to the global bit line, and that is configured to selectively connect the global bit line to a reference level responsive to a discharge control signal, and a discharge control circuit, that is connected to the discharge transistor via the discharge control signal, and that is configured to selectively disable the discharge transistor during an erase interval occurring before a verify interval of an erase verification operation carried out by the flash memory device.

    摘要翻译： 提供了一种闪存器件，其可以包括被配置为存储数据的存储器单元，连接到存储单元的局部位线，连接到本地位线的全局位线，连接到本地位线的放电晶体管 全局位线，并且被配置为响应于放电控制信号选择性地将全局位线连接到参考电平;以及放电控制电路，其通过放电控制信号连接到放电晶体管，并且被配置为 在由闪速存储器件执行的擦除验证操作的验证间隔之前的擦除间隔期间，选择性地禁用放电晶体管。

    Semiconductor memory device having hierarchical bit line structure and method of driving the semiconductor memory device
    8.
    发明授权
    Semiconductor memory device having hierarchical bit line structure and method of driving the semiconductor memory device 失效
    具有分级位线结构的半导体存储器件和驱动半导体存储器件的方法

    公开(公告)号：US08331162B2

    公开(公告)日：2012-12-11

    申请号：US12662222

    申请日：2010-04-06

    申请人： Jin-young Kim ,  Ki-whan Song

    发明人： Jin-young Kim ,  Ki-whan Song

    IPC分类号： G11C7/10

    CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/4097

    摘要： The semiconductor memory device includes a first memory cell array including at least one first memory cell and at least one second memory cell corresponding to the at least one first memory cell, a first low bit line connected to the at least one first memory cell, a first low complementary bit line connected to the at least one second memory cell, a first switch unit having a first terminal connected to the first low bit line, a second switch unit having a first terminal connected to the first low complementary bit line, a first global bit line connected to a second terminal of the first switch unit, a first global complementary bit line connected to a second terminal of the second switch unit, and a plurality of sensing amplifying units connected to the first global bit line and the first global complementary bit line.

    摘要翻译： 半导体存储器件包括第一存储器单元阵列，其包括至少一个第一存储单元和与该至少一个第一存储单元对应的至少一个第二存储单元，连接至该至少一个第一存储单元的第一低位线， 连接到所述至少一个第二存储器单元的第一低互补位线，具有连接到所述第一低位线的第一端子的第一开关单元，具有连接到所述第一低互补位线的第一端子的第二开关单元， 连接到第一开关单元的第二端子的全局位线，连接到第二开关单元的第二端子的第一全局互补位线以及连接到第一全局位线和第一全局互补位置的多个感测放大单元 位线。

    Method and apparatus for setting a lip region for lip reading
    9.
    发明授权
    Method and apparatus for setting a lip region for lip reading 有权
    用于设置唇部读数的唇部区域的方法和装置

    公开(公告)号：US08290277B2

    公开(公告)日：2012-10-16

    申请号：US12646600

    申请日：2009-12-23

    申请人： Seong-Taek Hwang ,  Jin-Young Kim

    发明人： Seong-Taek Hwang ,  Jin-Young Kim

    IPC分类号： G06K9/46

    CPC分类号： G06K9/00248

    摘要： A method for setting a lip region of a face included in an image, including setting a first region and a second region in an image including a face, identifying contrast information of the first region, setting a threshold for binarization using the contrast information, and binarizing the second region based on the threshold. A region in which a pixel having an identical binary value continuously distributed within a predetermined number of ranges in the binarized image is set as an eye candidate object. An eye region is then extracted from the eye candidate object based on geometric characteristic of an eye region in an image, and the lip region is set with reference to the extracted eye region based on geometric information of the eye region and the lip region.

    摘要翻译： 一种用于设置包括在图像中的脸部的唇部区域的方法，包括在包括脸部的图像中设置第一区域和第二区域，识别第一区域的对比度信息，使用对比度信息设置二值化阈值，以及 基于阈值二值化第二区域。 将其中在二值化图像中的预定数量范围内连续分布的相同二进制值的像素设置为候选对象的区域。 然后基于图像中的眼睛区域的几何特征，从眼睛候选物体中提取眼睛区域，并且基于眼睛区域和唇部区域的几何信息，参照提取的眼睛区域设定唇部区域。

    Semiconductor memory device comprising transistor having vertical channel structure
    10.
    发明授权
    Semiconductor memory device comprising transistor having vertical channel structure 失效
    半导体存储器件包括具有垂直沟道结构的晶体管

    公开(公告)号：US08274810B2

    公开(公告)日：2012-09-25

    申请号：US12955090

    申请日：2010-11-29

    申请人： Duk-Ha Park ,  Ki-Whan Song ,  Jin-Young Kim

    发明人： Duk-Ha Park ,  Ki-Whan Song ,  Jin-Young Kim

    IPC分类号： G11C5/02

    CPC分类号： H01L27/10876 ,  G11C7/1042 ,  G11C7/12 ,  G11C11/404 ,  G11C11/4094 ,  H01L29/78 ,  H01L29/7827

    摘要： A semiconductor memory device including a transistor having a vertical channel structure is provided. The device includes a first sub memory cell array including a first memory cell connected to a first bit lines and including a transistor having a vertical channel structure, a second sub memory cell array including a second memory cell connected to a first inverted bit lines and including a transistor having a vertical channel structure, and a plurality of precharge blocks. In addition, first and second precharge blocks are disposed at first and second sides of the first bit line and precharge the first bit line, and third and fourth precharge blocks are disposed at first and second sides of the first inverted bit line and precharge the first inverted bit line.

    摘要翻译： 提供一种包括具有垂直沟道结构的晶体管的半导体存储器件。 该器件包括第一子存储单元阵列，该第一子存储单元阵列包括连接到第一位线并包括具有垂直沟道结构的晶体管的第一存储单元，第二子存储单元阵列，包括连接到第一反相位线的第二存储单元， 具有垂直沟道结构的晶体管和多个预充电块。 此外，第一和第二预充电块设置在第一位线的第一和第二侧并对第一位线进行预充电，并且第三和第四预充电块设置在第一反相位线的第一和第二侧，并且对第一 反转位线。