公开(公告)号：US08830001B2

公开(公告)日：2014-09-09

申请号：US12134081

申请日：2008-06-05

申请人： Jingcheng Zhuang ,  Robert Bogdan Staszewski

发明人： Jingcheng Zhuang ,  Robert Bogdan Staszewski

IPC分类号： H03L7/085 ,  H03L7/089 ,  H03C5/00 ,  H03L7/081

CPC分类号： H03L7/0814 ,  H03C5/00 ,  H03L2207/50

摘要： A new all digital PLL (ADPLL) circuit and architecture and the corresponding method of implementation are provided. The ADPLL processes an integer and a fractional part of the phase signal separately, and achieves power reduction by disabling circuitry along the integer processing path of the circuit when the ADPLL loop is in a locked state. The integer processing path is automatically enabled when the loop is not in lock. Additional power savings is achieved by running the ADPLL on the lower-frequency master system clock, which also has the effect of reducing spur levels on the signals.

摘要翻译： 提供了全新的全数字PLL（ADPLL）电路和架构及相应的实现方法。 ADPLL分别处理相位信号的整数和分数部分，并且当ADPLL环路处于锁定状态时，通过沿电路的整数处理路径禁用电路来实现功率降低。 当循环未锁定时，整数处理路径自动启用。 通过在较低频率主系统时钟上运行ADPLL来实现额外的功率节省，这也具有减少信号上的杂散电平的作用。

公开(公告)号：US20130216003A1

公开(公告)日：2013-08-22

申请号：US13465057

申请日：2012-05-07

申请人： Jingcheng Zhuang ,  Nam V. Dang

发明人： Jingcheng Zhuang ,  Nam V. Dang

IPC分类号： H04L25/02

CPC分类号： H04L25/02 ,  H03K3/0322 ,  H03L7/0995 ,  H03L2207/06 ,  H04L7/033

摘要： Clock and data recovery (CDR) circuits and resettable voltage controlled oscillators (VCOs) are disclosed. In one embodiment, the CDR circuit includes a sampler configured to receive a data stream in a data path and sample the data stream. However, a clock signal of the data stream needs to be recovered to sample the data stream since the data stream may not be accompanied by the clock signal. To recover the clock signal from the data stream, the CDR circuit may have a resettable VCO configured to generate a clock output. The sampler and the resettable VCO may be operably associated so that the sampler samples the data stream in the data path based on the clock output. The resettable VCO can be reset to adjust a clock phase of the clock output and help reduce sampling errors resulting from drift of the clock output and/or the data stream.

摘要翻译： 公开了时钟和数据恢复（CDR）电路和可复位的压控振荡器（VCO）。 在一个实施例中，CDR电路包括被配置为在数据路径中接收数据流并对数据流进行采样的采样器。 然而，需要恢复数据流的时钟信号以采样数据流，因为数据流可能不伴随时钟信号。 为了从数据流恢复时钟信号，CDR电路可以具有被配置为产生时钟输出的可复位VCO。 采样器和可重置VCO可以可操作地相关联，使得采样器基于时钟输出对数据路径中的数据流进行采样。 可复位的VCO可以被复位以调整时钟输出的时钟相位，并有助于减少由于时钟输出和/或数据流的漂移而导致的采样错误。

公开(公告)号：US08461896B2

公开(公告)日：2013-06-11

申请号：US13155720

申请日：2011-06-08

申请人： Jingcheng Zhuang

发明人： Jingcheng Zhuang

IPC分类号： H03L5/00

CPC分类号： H03K3/356113 ,  H04B3/30

摘要： Techniques are disclosed relating to reducing wander created by AC couplers. In one embodiment, an integrated circuit is disclosed that includes an AC coupler and a DC-level shifter. The AC coupler is configured to receive a differential input signal at first and second nodes, and to shift a common-mode voltage of the differential input signal. The DC-level shifter is coupled to the first and second nodes, and configured to reduce wander of the AC coupler. In various embodiments, the DC-level shifter is configured to supply a differential reference signal to the AC coupler, and to create the differential reference signal from the differential input signal at the first and second nodes by changing a common-mode voltage of the differential input signal.

摘要翻译： 公开了关于减少由AC耦合器产生的漂移的技术。 在一个实施例中，公开了一种集成电路，其包括AC耦合器和DC电平移位器。 AC耦合器被配置为在第一和第二节点处接收差分输入信号，并且移位差分输入信号的共模电压。 DC电平移位器耦合到第一和第二节点，并且被配置为减少AC耦合器的漂移。 在各种实施例中，DC电平移位器被配置为向AC耦合器提供差分参考信号，并且通过改变差分的共模电压来产生来自第一和第二节点处的差分输入信号的差分参考信号 输入信号。

公开(公告)号：US07843275B1

公开(公告)日：2010-11-30

申请号：US11975457

申请日：2007-10-19

申请人： Tad Kwasniewski ,  Jingcheng Zhuang ,  Qingjin Du

发明人： Tad Kwasniewski ,  Jingcheng Zhuang ,  Qingjin Du

IPC分类号： H03K3/03 ,  H03L7/24

CPC分类号： H03L7/24 ,  H03K3/0315 ,  H03K3/0322 ,  H03K5/135

摘要： Frequency synthesizer circuitry employs a delay line. A reference clock signal propagates through successive stages of the delay line, and the currents drawn by output buffers of all of the stages are added at a common node. The common node current is converted to a voltage, which is AC-coupled to an output buffer ring oscillator of the frequency synthesizer. The output buffer ring oscillator includes a plurality of inverters connected in a series. A feedback connection including a resistor is provided from an output node of the last inverter to an input node of the first inverter.

摘要翻译： 频率合成器电路采用延迟线。 参考时钟信号通过延迟线的连续级传播，并且所有级的输出缓冲器所绘制的电流在公共节点处相加。 公共节点电流被转换为与该频率合成器的输出缓冲环形振荡器AC耦合的电压。 输出缓冲环形振荡器包括串联连接的多个反相器。 从最后一个逆变器的输出节点向第一反相器的输入节点提供包括电阻器的反馈连接。

公开(公告)号：US20100027729A1

公开(公告)日：2010-02-04

申请号：US12411482

申请日：2009-03-26

申请人： Thomas Casimir Murphy ,  Jingcheng Zhuang ,  Khurram Waheed ,  Roman Staszewski

发明人： Thomas Casimir Murphy ,  Jingcheng Zhuang ,  Khurram Waheed ,  Roman Staszewski

IPC分类号： H04L7/00

CPC分类号： H04W56/0045

摘要： Transmission of information between user equipment (UE) and base stations in a wireless network occurs using a stream of periodic data. A modem in the UE operates synchronized to a first clock source to produce the stream of periodic data at a chip rate. Transceiver circuitry is synchronized to a variable clock source to receive the stream of data from the first circuitry at a rate according to the variable clock source. A fixed phase relationship is maintained between the variable clock source and the first clock source while the data period is uniform by adjusting the variable clock in response to detected phase errors. Occasionally, one period of the periodic data is changed by a defined amount. The fixed phase relationship is restored over a number of periods in a gradual manner by changing the frequency of the variable clock by an amount. By restoring the phase relationship gradually, quality degradation of the transmitted signal is reduced.

摘要翻译： 使用周期性数据流在无线网络中的用户设备（UE）与基站之间传输信息。 UE中的调制解调器与第一时钟源同步，以码片速率产生周期性数据流。 收发器电路与可变时钟源同步，以根据可变时钟源的速率从第一电路接收数据流。 通过根据检测到的相位误差调整可变时钟，在可变时钟源和第一时钟源之间保持固定的相位关系，同时数据周期是均匀的。 有时，周期性数据的一个周期被改变一定的量。 通过将可变时钟的频率改变一定量，以逐渐的方式在多个周期内恢复固定相位关系。 通过逐渐恢复相位关系，传输信号的质量劣化降低。

公开(公告)号：US20130191679A1

公开(公告)日：2013-07-25

申请号：US13420800

申请日：2012-03-15

申请人： Jingcheng Zhuang ,  Nam V. Dang ,  Xiaohua Kong ,  Zhi Zhu ,  Tirdad Sowlati ,  Behnam Amelifard

发明人： Jingcheng Zhuang ,  Nam V. Dang ,  Xiaohua Kong ,  Zhi Zhu ,  Tirdad Sowlati ,  Behnam Amelifard

IPC分类号： G06F1/24

CPC分类号： H03L7/0807 ,  H03L7/087 ,  H03L7/091 ,  H03L7/14 ,  H04L7/0004 ,  H04L7/033

摘要： A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.

摘要翻译： 时钟/数据恢复电路包括边沿检测器电路，其可操作以接收串行数据脉冲串并响应于串行数据脉冲串的第一个边沿而产生复位信号。 时钟/数据恢复电路还可以包括耦合到边缘检测器电路的振荡器。 振荡器在接收到串行数据脉冲串之前锁定到目标数据速率上，并响应于复位信号锁定到串行数据脉冲串的相位上。 时钟/数据恢复电路还可以包括接收串行数据突发的相位检测器电路。 相位检测器电路耦合到振荡器。 相位检测器电路调节振荡器以在串行数据突发期间保持锁定到串行数据突发的相位。

公开(公告)号：US20120133459A1

公开(公告)日：2012-05-31

申请号：US12955040

申请日：2010-11-29

申请人： Jingcheng Zhuang ,  Bruce A. Doyle ,  Emerson S. Fang

发明人： Jingcheng Zhuang ,  Bruce A. Doyle ,  Emerson S. Fang

IPC分类号： H04B3/14

CPC分类号： H04B3/14 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/03878

摘要： An apparatus includes a capacitor coupled between a first node responsive to receive an input signal and a second node. The apparatus includes a first circuit coupled to the second node and a third node. The first circuit is selectively operable to separately configure at least one of a low-frequency gain of an equalizer and a pole of the equalizer. The equalizer includes the first circuit and the capacitor. The second node is responsive to receive an equalized version of an AC signal of the input signal in a first mode of the apparatus. The second node is responsive to receive a non-equalized version of the AC signal of the input signal in a second mode of the apparatus. The equalized version of the AC signal of the input signal may be a level-shifted and equalized version of the AC signal in the first mode of the apparatus.

摘要翻译： 一种装置包括耦合在响应于接收输入信号的第一节点和第二节点之间的电容器。 该装置包括耦合到第二节点和第三节点的第一电路。 第一电路可选择性地操作以分别配置均衡器的低频增益和均衡器的极点中的至少一个。 均衡器包括第一电路和电容器。 第二节点响应于在装置的第一模式中接收输入信号的AC信号的均衡版本。 第二节点响应于在设备的第二模式中接收输入信号的AC信号的非均衡版本。 输入信号的AC信号的均衡版本可以是装置的第一模式中的AC信号的电平移位和均衡版本。

公开(公告)号：US08839020B2

公开(公告)日：2014-09-16

申请号：US13420800

申请日：2012-03-15

申请人： Jingcheng Zhuang ,  Nam V. Dang ,  Xiaohua Kong ,  Zhi Zhu ,  Tirdad Sowlati ,  Behnam Amelifard

发明人： Jingcheng Zhuang ,  Nam V. Dang ,  Xiaohua Kong ,  Zhi Zhu ,  Tirdad Sowlati ,  Behnam Amelifard

IPC分类号： G06F1/04 ,  G06F1/12 ,  H03L7/00 ,  H04B7/212 ,  H04L12/28 ,  H04J3/06 ,  H04L7/00 ,  H04B1/16 ,  G06F15/16

CPC分类号： H03L7/0807 ,  H03L7/087 ,  H03L7/091 ,  H03L7/14 ,  H04L7/0004 ,  H04L7/033

摘要： A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.

摘要翻译： 时钟/数据恢复电路包括边沿检测器电路，其可操作以接收串行数据脉冲串并且响应于串行数据脉冲串的第一个边沿而产生复位信号。 时钟/数据恢复电路还可以包括耦合到边缘检测器电路的振荡器。 振荡器在接收到串行数据脉冲串之前锁定到目标数据速率上，并响应于复位信号锁定到串行数据脉冲串的相位上。 时钟/数据恢复电路还可以包括接收串行数据突发的相位检测器电路。 相位检测器电路耦合到振荡器。 相位检测器电路调节振荡器以在串行数据突发期间保持锁定到串行数据突发的相位。

公开(公告)号：US20130127507A1

公开(公告)日：2013-05-23

申请号：US13300089

申请日：2011-11-18

申请人： Jingcheng Zhuang

发明人： Jingcheng Zhuang

IPC分类号： H03K3/3565 ,  H03K3/3562 ,  H03K3/356

CPC分类号： H03K3/356139 ,  H03K3/35625

摘要： A low-hysteresis high-speed latch circuit is disclosed which isolates a sample stage and hold stage from one another during a latch clock phase and simultaneously shorts the output nodes together during the latch clock phase to reduce hysteresis of the latch.

摘要翻译： 公开了一种低滞后高速锁存电路，其在锁存时钟相位期间将采样级和保持级彼此隔离，并且在锁存时钟相位期间同时将输出节点短路在一起以减少锁存器的滞后。

公开(公告)号：US08319579B2

公开(公告)日：2012-11-27

申请号：US12955040

申请日：2010-11-29

申请人： Jingcheng Zhuang ,  Bruce A. Doyle ,  Emerson S. Fang

发明人： Jingcheng Zhuang ,  Bruce A. Doyle ,  Emerson S. Fang

IPC分类号： H04B3/04

CPC分类号： H04B3/14 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/03878

摘要： An apparatus includes a capacitor coupled between a first node responsive to receive an input signal and a second node. The apparatus includes a first circuit coupled to the second node and a third node. The first circuit is selectively operable to separately configure at least one of a low-frequency gain of an equalizer and a pole of the equalizer. The equalizer includes the first circuit and the capacitor. The second node is responsive to receive an equalized version of an AC signal of the input signal in a first mode of the apparatus. The second node is responsive to receive a non-equalized version of the AC signal of the input signal in a second mode of the apparatus. The equalized version of the AC signal of the input signal may be a level-shifted and equalized version of the AC signal in the first mode of the apparatus.

摘要翻译： 一种装置包括耦合在响应于接收输入信号的第一节点和第二节点之间的电容器。 该装置包括耦合到第二节点和第三节点的第一电路。 第一电路可选择性地操作以分别配置均衡器的低频增益和均衡器的极点中的至少一个。 均衡器包括第一电路和电容器。 第二节点响应于在装置的第一模式中接收输入信号的AC信号的均衡版本。 第二节点响应于在设备的第二模式中接收输入信号的AC信号的非均衡版本。 输入信号的AC信号的均衡版本可以是装置的第一模式中的AC信号的电平移位和均衡版本。