公开(公告)号：US06727589B2

公开(公告)日：2004-04-27

申请号：US09725862

申请日：2000-11-30

申请人： Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

发明人： Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

IPC分类号： H01L2348

CPC分类号： H01L21/76843 ,  H01L21/31116 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/7684

摘要： A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.

摘要翻译： 一种通过氧化FOX绝缘体的侧壁来保护半导体中的可流动的氧化物绝缘体的方法和结构，可选地将氧化的FOX侧壁氮化，然后覆盖包括侧壁在内的FOX绝缘体中的槽或多个槽的所有表面， 导电二级保护层。 在多层镶嵌结构中，FOX绝缘体的表面也被氧化，在其上沉积另外的氧化物层，并且沉积在氧化物层上的氮化物层。 然后重复步骤以获得可比较的镶嵌结构。 材料可以变化，并且每个镶嵌层可以是单镶嵌层或双镶嵌层。

公开(公告)号：US06348736B1

公开(公告)日：2002-02-19

申请号：US09429257

申请日：1999-10-29

申请人： Vincent J. McGahay ,  John P. Hummel ,  Joyce Liu ,  Rebecca Mih ,  Kamalesh Srivastava ,  Robert Cook ,  Stephen E. Greco

发明人： Vincent J. McGahay ,  John P. Hummel ,  Joyce Liu ,  Rebecca Mih ,  Kamalesh Srivastava ,  Robert Cook ,  Stephen E. Greco

IPC分类号： H01L2348

CPC分类号： H01L21/76831 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/31144 ,  H01L21/3122 ,  H01L21/3124 ,  H01L21/76807

摘要： Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. A first protective layer is formed in situ on the dielectric material, such as by exposing the material to an oxygen-containing or flourine containing plasma. Also, by performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. The first protective layer and the surface protective covering can be formed by essentially identical processes. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.

摘要翻译： 抗蚀剂显影剂可以攻击一些先进的介电材料，例如可以用作集成电路芯片的表面和形成在介电材料表面上的布线层之间的绝缘体的倍半硅氧烷材料。 在电介质材料上原位形成第一保护层，例如通过将材料暴露于含氧或含氟的等离子体中。 此外，通过进行抗蚀剂剥离或蚀刻工艺，其中将反应物材料从电介质材料外部供应或从电介质材料释放出来，可以形成非常薄的中间材料的表面保护覆盖层，其不能抵抗显影剂或多个 可能损坏可流动的氧化物材料的其他材料。 第一保护层和表面保护层可以通过基本相同的方法形成。 因此，与芯片形成牢固的连接和通孔的双镶嵌工艺可以与具有特别低介电常数的先进电介质相兼容，以最小化导体电容并支持快速的信号传播和抗噪声性，即使导体彼此间隔紧密。

公开(公告)号：US06479884B2

公开(公告)日：2002-11-12

申请号：US09893786

申请日：2001-06-29

申请人： Robert Cook ,  Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

发明人： Robert Cook ,  Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

IPC分类号： H01L2358

CPC分类号： H01L21/76808 ,  H01L2221/1063

摘要： Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.

摘要翻译： 抗蚀剂显影剂可以攻击一些先进的介电材料，例如可以用作集成电路芯片的表面和形成在介电材料表面上的布线层之间的绝缘体的倍半硅氧烷材料。 通过进行抗蚀剂剥离或蚀刻工艺，其中将反应物材料从电介质材料外部供应或释放出来，可以形成非常薄的中间材料的表面保护覆盖层，其不能抵抗显影剂或多种其它材料 这可能会损坏可流动的氧化物材料。 因此，与芯片形成牢固的连接和通孔的双镶嵌工艺可以与具有特别低介电常数的先进电介质相兼容，以最小化导体电容并支持快速的信号传播和抗噪声性，即使导体彼此间隔紧密。

公开(公告)号：US06329280B1

公开(公告)日：2001-12-11

申请号：US09311470

申请日：1999-05-13

申请人： Robert Cook ,  Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

发明人： Robert Cook ,  Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L2221/1063

摘要： Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.

公开(公告)号：US06221780B1

公开(公告)日：2001-04-24

申请号：US09408351

申请日：1999-09-29

申请人： Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

发明人： Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

IPC分类号： H01L21311

CPC分类号： H01L21/76843 ,  H01L21/31116 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/7684

摘要： A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.

摘要翻译： 一种通过氧化FOX绝缘体的侧壁来保护半导体中的可流动的氧化物绝缘体的方法和结构，可选地将氧化的FOX侧壁氮化，然后覆盖包括侧壁在内的FOX绝缘体中的槽或多个槽的所有表面， 导电二级保护层。 在多层镶嵌结构中，FOX绝缘体的表面也被氧化，在其上沉积另外的氧化物层，并且沉积在氧化物层上的氮化物层。 然后重复步骤以获得可比较的镶嵌结构。 材料可以变化，并且每个镶嵌层可以是单镶嵌层或双镶嵌层。

公开(公告)号：US08129286B2

公开(公告)日：2012-03-06

申请号：US12139803

申请日：2008-06-16

申请人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/302 ,  B44C1/22

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

摘要翻译： 制造半导体器件结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在该绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成 亚光刻特征跨越至少一个互连的侧壁。

公开(公告)号：US07948083B2

公开(公告)日：2011-05-24

申请号：US11763135

申请日：2007-06-14

申请人： Christos D. Dimitrakopoulos ,  Stephen M. Gates ,  Vincent J. McGahay ,  Sanjay C. Mehta

发明人： Christos D. Dimitrakopoulos ,  Stephen M. Gates ,  Vincent J. McGahay ,  Sanjay C. Mehta

IPC分类号： H01L29/40

CPC分类号： H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of chemical mechanical polishing and UV exposure or chemical repair treatment which steps improve the reliability of the interconnect structure formed. The present invention also relates to an interconnect structure which include a porous ultra low k dielectric of the SiCOH type in which the surface layer thereof has been modified so as to form a gradient layer that has both a density gradient and a C content gradient.

摘要翻译： 本发明涉及改进单镶嵌型或双镶嵌型互连结构的制造方法，其中在制造之后金属线之间没有硬掩模保持或导电性问题。 本发明的方法至少包括化学机械抛光和UV曝光或化学修复处理的步骤，这些步骤提高了形成的互连结构的可靠性。 本发明还涉及一种互连结构，其包括SiCOH型的多孔超低k电介质，其中其表面层被修饰以形成具有密度梯度和C含量梯度的梯度层。

公开(公告)号：US20100200960A1

公开(公告)日：2010-08-12

申请号：US12689479

申请日：2010-01-19

申请人： Matthew S. Angyal ,  Lawrence A. Clevenger ,  Vincent J. McGahay ,  Satyanarayana V. Nitta ,  Shaoning Yao

发明人： Matthew S. Angyal ,  Lawrence A. Clevenger ,  Vincent J. McGahay ,  Satyanarayana V. Nitta ,  Shaoning Yao

IPC分类号： H01L23/544 ,  H01L21/302

CPC分类号： H01L23/585 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Deep trenches formed beneath contact level in a semiconductor substrate function as crackstops, in a die area or in a scribe area of the wafer, and may be disposed in rows of increasing distance from a device which they are intended to protect, and may be located under a lattice work crackstop structure in an interconnect stack layer. The deep trenches may remain unfilled, or may be filled with a dielectric material or conductor. The deep trenches may have a depth into the substrate of approximately 1 micron to 100 microns, and a width of approximately 10 nm to 10 microns.

摘要翻译： 形成在半导体衬底的接触电平下方的深沟槽作为裂纹，在晶片的管芯区域或划线区域中起作用，并且可以设置成距它们旨在保护的器件的距离增加的行，并且可以位于 在互连堆叠层中的格子工作裂纹结构下。 深沟槽可以保持未填充，或者可以用介电材料或导体填充。 深沟槽可以具有大约1微米至100微米的衬底的深度和约10nm至10微米的宽度。

公开(公告)号：US20090149979A1

公开(公告)日：2009-06-11

申请号：US11951503

申请日：2007-12-06

申请人： Vincent J. McGahay

发明人： Vincent J. McGahay

IPC分类号： G06F19/00

CPC分类号： G06Q10/06

摘要： Disclosed herein are embodiments of an automated manufacturing system that is used to process multiple jobs in a product fabrication environment, where such processing comprises performing the same multiple consecutive process steps for each job and where each process step can be accomplished using one or more different available processing tools. The manufacturing system incorporates a unique run-time dispatch system. This dispatch system schedules the order in which jobs will be processed and further randomly assigns a particular combination of process steps and tools to each job in such a way that the processing tools are evenly distributed across the jobs. Ensuring even distribution of processing tools allows a statistical process control system to not only detect, for a given process step, product variability outside desired specifications, but also to efficiently de-convolve such product variability.

摘要翻译： 这里公开的是用于在产品制造环境中处理多个作业的自动化制造系统的实施例，其中这样的处理包括为每个作业执行相同的多个连续的处理步骤，并且其中每个处理步骤可以使用一个或多个不同的可用 加工工具。 制造系统采用独特的运行时调度系统。 该调度系统调度处理作业的顺序，并进一步随机地将每个作业的特定组合处理步骤和工具分配给处理工具均匀地分布在作业中。 确保加工工具的均匀分配允许统计过程控制系统不仅针对给定的工艺步骤检测出期望规格之外的产品变异性，而且还有效地解除这种产品变异性。

公开(公告)号：US07439151B2

公开(公告)日：2008-10-21

申请号：US11531298

申请日：2006-09-13

申请人： Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer Eshun ,  Vincent J. McGahay ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer Eshun ,  Vincent J. McGahay ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L21/20

CPC分类号： H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for integrating the formation of metal-insulator-metal (MIM) capacitors within dual damascene processing includes forming a lower interlevel dielectric (ILD) layer having a lower capacitor electrode and one or more lower metal lines therein, the ILD layer having a first dielectric capping layer formed thereon. An upper ILD layer is formed over the lower ILD layer, and a via and upper line structure are defined within the upper ILD layer. The via and upper line structure are filled with a planarizing layer, followed by forming and patterning a resist layer over the planarizing layer. An upper capacitor electrode structure is defined in the upper ILD layer corresponding to a removed portion of the resist. The via, upper line structure and upper capacitor electrode structure are filled with conductive material, wherein a MIM capacitor is defined by the lower capacitor electrode, first dielectric capping layer and upper capacitor electrode structure.

摘要翻译： 一种用于在双镶嵌加工中整合金属 - 绝缘体 - 金属（MIM）电容器的形成的方法包括在其中形成具有较低电容器电极和一个或多个下部金属线的较低层间电介质（ILD）层，所述ILD层具有第一 在其上形成介电覆盖层。 上ILD层形成在下ILD层上，并且通孔和上线结构限定在上ILD层内。 通孔和上线结构填充有平坦化层，然后在平坦化层上形成和图案化抗蚀剂层。 上部电容器电极结构限定在对应于抗蚀剂的去除部分的上部ILD层中。 通孔，上线结构和上电容器电极结构填充有导电材料，其中MIM电容器由下电容器电极，第一介电覆盖层和上电容器电极结构限定。