公开(公告)号：US20100315118A1

公开(公告)日：2010-12-16

申请号：US12860004

申请日：2010-08-20

申请人： Jonathan W. Greene ,  John McCollum ,  Volker Hecht

发明人： Jonathan W. Greene ,  John McCollum ,  Volker Hecht

IPC分类号： H03K19/00

CPC分类号： H03K19/17764 ,  G01R31/318519 ,  H03K19/17736

摘要： An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.

摘要翻译： FPGA架构包括具有非易失性开关的多路复用器，其具有耦合到字线W的控制栅极，与行相关联的每个字线，所述开关通过具有可控接地连接NGND的缓冲器连接到布线轨道，至少一些开关是 连接开关可耦合到多个位线B中的一个，每个位线与列相关联。

公开(公告)号：US07816946B1

公开(公告)日：2010-10-19

申请号：US12360948

申请日：2009-01-28

申请人： Volker Hecht ,  Fei Li ,  Jonathan W. Greene

发明人： Volker Hecht ,  Fei Li ,  Jonathan W. Greene

IPC分类号： G06F7/38 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/1778

摘要： A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.

摘要翻译： 公开了一种用于现场可编程门阵列集成电路器件的触发器。 触发器包括耦合到第一可编程路由元件的数据输出端子，耦合到第二可编程路由元件的数据输入端子和时钟输入端子，其中响应于施加的信号在数据输出端子出现的信号 时钟输入端子相对于施加到数据输入端子的相应逻辑信号具有相反的逻辑极性。

公开(公告)号：US5781033A

公开(公告)日：1998-07-14

申请号：US754188

申请日：1996-11-12

申请人： Douglas C. Galbraith ,  Abbas El Gamal ,  Jonathan W. Greene

发明人： Douglas C. Galbraith ,  Abbas El Gamal ,  Jonathan W. Greene

IPC分类号： H03K3/037 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1737 ,  H03K3/037

摘要： A logic module includes first and second multiplexers each having two data inputs and a select input. Both select inputs are connected to the output of a two-input logic gate of a first type. The inputs to the first and second multiplexers comprise data signals from a first group. One input of each logic gate comprises a data signal of a second group and the other input of each logic gate comprises a data signal of a third group. A third multiplexer has first and second data inputs connected the outputs of the first and second multiplexers, respectively, and a select input connected to the output of a two-input logic gate of a second type. Its output is connected to a first data input of a fourth multiplexer having a HOLD1 input coupled to its select input. Its output and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth multiplexer and to the first data input of a fifth multiplexer. The fifth multiplexer select input comprises a HOLD2 input. Its output and the CLEAR input are presented to an AND gate whose output is connected to the second data input of the fifth multiplexer and to an output node. The CLEAR, HOLD1 and HOLD2 inputs comprise combinations of signals from a data signal of a third group which may contain data signals of one of the other groups.

摘要翻译： 逻辑模块包括具有两个数据输入和选择输入的第一和第二多路复用器。 两个选择输入都连接到第一类型的双输入逻辑门的输出。 第一和第二多路复用器的输入包括来自第一组的数据信号。 每个逻辑门的一个输入包括第二组的数据信号，并且每个逻辑门的另一个输入包括第三组的数据信号。 第三复用器具有分别连接第一和第二多路复用器的输出的第一和第二数据输入以及连接到第二类型的双输入逻辑门的输出的选择输入。 其输出连接到具有耦合到其选择输入的HOLD1输入的第四多路复用器的第一数据输入。 其输出和CLEAR输入被呈现给AND门，其输出连接到第四多路复用器的第二数据输入端和第五多路复用器的第一数据输入端。 第五多路复用器选择输入包括一个HOLD2输入。 其输出和CLEAR输入被提供给AND门，其输出连接到第五多路复用器的第二数据输入端和输出节点。 CLEAR，HOLD1和HOLD2输入包括来自第三组的数据信号的信号的组合，其可以包含其他组之一的数据信号。

公开(公告)号：US5055718A

公开(公告)日：1991-10-08

申请号：US522232

申请日：1990-05-11

申请人： Douglas C. Galbraith ,  Abbas El Gamal ,  Jonathan W. Greene

发明人： Douglas C. Galbraith ,  Abbas El Gamal ,  Jonathan W. Greene

IPC分类号： G06F17/10 ,  H03K3/037 ,  H03K19/173

CPC分类号： H03K19/1737 ,  H03K3/037

摘要： A logic module includes a first and a second two-input multiplexer each having first and second data inputs. Both the first and second multiplexer include a select input, both of which are connected to the output of a two-input logic gate of a first type having first and second data inputs. The inputs to the first and second two-input multiplexers are sourced with data signals from a first group. One input of each of the logic gates is sourced from a data signal of a second group and the other input of each of the logic gates is sourced from a data signal of a third group. A third two-input multiplexer has its first and second data inputs connected the outputs of the first and second multiplexers, respectively. A select input of the third two-input multiplexer is connected to the output of a two-input logic gate of a second type having first and second data inputs.The output of the third two-input multiplexer is connected to a first data input of a fourth two-input multiplexer having a HOLD1 input coupled to its select input. Its output is and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth two-input multiplexer and to the first data input of a fifth two-input multiplexer. The select input of the fifth two-input multiplexer is connected to a HOLD2 input. Its output and the CLEAR input are presented to an AND gate whose output is connected to the second data input of the fifth two-input multiplexer and to an output node. The CLEAR, HOLD1 and HOLD2 inputs are defined by combinations of signals from a data signal of a third group which may contain a data siganl of one of the other groups.

公开(公告)号：US4873459A

公开(公告)日：1989-10-10

申请号：US195728

申请日：1988-05-18

申请人： Abbas A. El Gamal ,  Khaled A. El-Ayat ,  Jonathan W. Greene ,  Ta-Pen R. Guo ,  Justin M. Reyneri

发明人： Abbas A. El Gamal ,  Khaled A. El-Ayat ,  Jonathan W. Greene ,  Ta-Pen R. Guo ,  Justin M. Reyneri

IPC分类号： G01R31/3185 ,  H03K19/177

CPC分类号： H03K19/17748 ,  G01R31/318516 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17796

摘要： A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segements connected by normally open programmable elements situated at the intersection of any two segments to be connected. Sensing circuitry and wiring may be included to allow 100% observability of internal circuit nodes, such as module outputs, from an external pad interface. A universal function module may be configured to implement the popular logic functions and has a physical layout which is conducive to custom circuit design.

摘要翻译： 公开了可用于数字和模拟系统设计的逻辑阵列的用户可编程互连体系结构。 在一个实施例中，矩阵中的多个逻辑单元或模块通过垂直和水平布线通道连接。 接线通道可以由用户编程，以互连各种逻辑单元以实现所需的逻辑功能。 布线通道包括通过常开的可编程元件连接的布线段，位于要连接的任何两个段的交点处。 可以包括感应电路和接线，以允许来自外部接口接口的内部电路节点（如模块输出）的100％可观察性。 通用功能模块可以被配置为实现流行的逻辑功能并且具有有利于定制电路设计的物理布局。

公开(公告)号：US20100156457A1

公开(公告)日：2010-06-24

申请号：US12340358

申请日：2008-12-19

申请人： Jonathan W. Greene ,  Gregory Bakker ,  Vidyadhara Bellippady ,  Volker Hecht ,  Theodore Speers

发明人： Jonathan W. Greene ,  Gregory Bakker ,  Vidyadhara Bellippady ,  Volker Hecht ,  Theodore Speers

IPC分类号： H03K19/177 ,  H03K19/0175

CPC分类号： H03K19/17784

摘要： A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.

摘要翻译： 公开了具有多个可编程区域的可编程逻辑器件（PLD）。 一些可编程区域具有开关电源或接地电源，以允许它们在一个或多个低功率模式下进入低功率状态。 在低功率模式期间，至少一个可编程区域始终保持接通状态，以使用户能够设计定制的PLD功率管理逻辑，该逻辑可以放置在永久可编程区域中。

公开(公告)号：US07463061B1

公开(公告)日：2008-12-09

申请号：US11185426

申请日：2005-07-19

申请人： Jonathan W. Greene ,  Vidya Bellippady

发明人： Jonathan W. Greene ,  Vidya Bellippady

IPC分类号： H03K19/20

CPC分类号： H03K19/0008

摘要： A reduced-leakage interconnect circuit includes a buffer having an input and an output, at least one multiplexer transistor coupled between a multiplexer input node and the input of the buffer, and a fixed-state multiplexer transistor coupled between a fixed-state multiplexer input node and the input of the buffer, the fixed-state multiplexer input node having a potential of either less than zero volts or more than VCC present on it.

摘要翻译： 减少泄漏的互连电路包括具有输入和输出的缓冲器，耦合在多路复用器输入节点和缓冲器的输入之间的至少一个多路复用器晶体管，以及耦合在固定状态多路复用器输入节点 以及缓冲器的输入，固定状态多路复用器输入节点具有小于零伏特或高于其上存在的VCC的电位。

公开(公告)号：US07430137B2

公开(公告)日：2008-09-30

申请号：US11868694

申请日：2007-10-08

申请人： Jonathan W. Greene ,  Fethi Dhaoui ,  Robert M. Salter, III ,  John McCollum

发明人： Jonathan W. Greene ,  Fethi Dhaoui ,  Robert M. Salter, III ,  John McCollum

IPC分类号： G11C16/02 ,  G11C5/02 ,  G11C5/06 ,  G06F7/38 ,  H03K19/173 ,  H03K19/177 ,  H03K19/94

CPC分类号： H03K19/1776 ,  G11C16/0441 ,  H03K19/17736 ,  H03K19/1778

摘要： A non-volatile memory cell comprises a first floating gate transistor having a source, a drain, and a gate electrically coupled to a row line. A second floating gate transistor has a source, a drain, and a gate electrically coupled to the row line. A first p-channel MOS transistor has a source, a drain, and a gate, the drain of the first p-channel MOS transistor electrically coupled to the drain of the first floating gate transistor forming a first common node. A second p-channel MOS transistor has a source, a drain, and a gate, the first drain of the second p-channel MOS transistor electrically coupled to the drain of the second floating gate transistor forming a second common node, the gate of the second p-channel MOS transistor electrically coupled to the first common node, and the second common node electrically coupled to the gate of the first p-channel MOS transistor.

摘要翻译： 非易失性存储单元包括具有电耦合到行线的源极，漏极和栅极的第一浮栅晶体管。 第二浮栅晶体管具有电耦合到行线的源极，漏极和栅极。 第一p沟道MOS晶体管具有源极，漏极和栅极，第一p沟道MOS晶体管的漏极电耦合到第一浮动栅极晶体管的漏极，形成第一公共节点。 第二p沟道MOS晶体管具有源极，漏极和栅极，第二p沟道MOS晶体管的第一漏极电耦合到形成第二公共节点的第二浮栅晶体管的漏极，栅极 电耦合到第一公共节点的第二P沟道MOS晶体管，以及电耦合到第一p沟道MOS晶体管的栅极的第二公共节点。

公开(公告)号：US5610534A

公开(公告)日：1997-03-11

申请号：US505830

申请日：1995-05-18

申请人： Douglas C. Galbraith ,  Abbas El Gamal ,  Jonathan W. Greene

发明人： Douglas C. Galbraith ,  Abbas El Gamal ,  Jonathan W. Greene

IPC分类号： H03K3/037 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1737 ,  H03K3/037

摘要： A logic module includes first and second multiplexers each having two data inputs and a select input. Both select inputs are connected to the output of a two-input logic gate of a first type. The inputs to the first and second multiplexers comprise data signals from a first group. One input of each logic gate comprises a data signal of n second group and the other input of each logic gate comprises a data signal of a third group. A third multiplexer has first and second data inputs connected the outputs of the first and second multiplexers, respectively, and a select input connected to the output of a two-input logic gate of a second type. Its output is connected to a first data input of a fourth-multiplexer having a HOLD1 input coupled to its select input. Its output and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth multiplexer and to the first data input of a fifth multiplexer. The fifth multiplexer select input comprises a HOLD2 input. Its output and the CLEAR input ere presented to an AND gate whose output is connected to the second data input of the fifth multiplexer and to an output node. The CLEAR, HOLD1 and HOLD2 inputs comprise combinations of signals from a data signal of a third group which may contain data signals of one of the other groups.

摘要翻译： 逻辑模块包括具有两个数据输入和选择输入的第一和第二多路复用器。 两个选择输入都连接到第一类型的双输入逻辑门的输出。 第一和第二多路复用器的输入包括来自第一组的数据信号。 每个逻辑门的一个输入包括n个第二组的数据信号，并且每个逻辑门的另一个输入包括第三组的数据信号。 第三复用器具有分别连接第一和第二多路复用器的输出的第一和第二数据输入以及连接到第二类型的双输入逻辑门的输出的选择输入。 其输出连接到具有耦合到其选择输入的HOLD1输入的第四多路复用器的第一数据输入。 其输出和CLEAR输入被呈现给AND门，其输出连接到第四多路复用器的第二数据输入端和第五多路复用器的第一数据输入端。 第五多路复用器选择输入包括一个HOLD2输入。 其输出和CLEAR输入被提供给AND门，其输出连接到第五多路复用器的第二数据输入端和输出节点。 CLEAR，HOLD1和HOLD2输入包括来自第三组的数据信号的信号的组合，其可以包含其他组之一的数据信号。

公开(公告)号：US5198705A

公开(公告)日：1993-03-30

申请号：US773353

申请日：1991-10-07

申请人： Douglas C. Galbraith ,  Abbas El Gamal ,  Jonathan W. Greene

发明人： Douglas C. Galbraith ,  Abbas El Gamal ,  Jonathan W. Greene

IPC分类号： H03K3/037 ,  H03K19/173

CPC分类号： H03K19/1737 ,  H03K3/037

摘要： A logic module includes first and second multiplexers each having two data inputs and a select input. Both select inputs are connected to the output of a two-input logic gate of a first type. The inputs to the first and second multiplexers comprise data signals from a first group. One input of each logic gate comprises a data signal of a second group and the other input of each logic gate comprises a data signal of a third group. A third multiplexer has first and second data inputs connected the outputs of the first and second multiplexers, respectively, and a select input connected to the output of a two-input logic gate of a second type. Its output is connected to a first data input of a fourth multiplexer having a HOLD1 input coupled to its select input. Its output and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth multiplexer and to the first data input of a fifth multiplexer. The fifth multiplexer select input comprises a HOLD2 input. Its output and the CLEAR input are presented to an AND gate whose output is connected to the second data input of the fifth multiplexer and to an output node. The CLEAR, HOLD1 and HOLD2 inputs comprise combinations of signals from a data signal of a third group which may contain data signals of one of the other groups.

摘要翻译： 逻辑模块包括具有两个数据输入和选择输入的第一和第二多路复用器。 两个选择输入都连接到第一类型的双输入逻辑门的输出。 第一和第二多路复用器的输入包括来自第一组的数据信号。 每个逻辑门的一个输入包括第二组的数据信号，并且每个逻辑门的另一个输入包括第三组的数据信号。 第三复用器具有分别连接第一和第二多路复用器的输出的第一和第二数据输入以及连接到第二类型的双输入逻辑门的输出的选择输入。 其输出连接到具有耦合到其选择输入的HOLD1输入的第四多路复用器的第一数据输入。 其输出和CLEAR输入被呈现给AND门，其输出连接到第四多路复用器的第二数据输入端和第五多路复用器的第一数据输入端。 第五多路复用器选择输入包括一个HOLD2输入。 其输出和CLEAR输入被提供给AND门，其输出连接到第五多路复用器的第二数据输入端和输出节点。 CLEAR，HOLD1和HOLD2输入包括来自第三组的数据信号的信号的组合，其可以包含其他组之一的数据信号。