公开(公告)号：US20060187724A1

公开(公告)日：2006-08-24

申请号：US10548340

申请日：2004-03-03

申请人： Jose Pineda De Gyvez ,  Manoj Sachdev ,  Andrei Pavlov

发明人： Jose Pineda De Gyvez ,  Manoj Sachdev ,  Andrei Pavlov

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C2029/5006

摘要： A method and apparatus for testing a static random access memory (SRAM) array for the presence of weak defects. A 0/1 ratio is first written to the memory array (step 100), following which the bit lines BL and BLB are pre-charged and equalized to a threshold detection voltage (step 102). The threshold detection voltage is programmed according to the 0/1 ratio of cells, so as to take into account specific cell criterion and/or characteristics. Next, the word lines associated with all of the cells in the array are enabled substantially simultaneously (step 104), the bit lines are then shorted together (step 106), the word lines are disabled (step 108) and the bit lines are released (step 110). Following these steps, the contents of the SRAM array are read and compared against the original 0/1 ratio (step 112). 10 Any cells whose contents do not match the original 0/1 ratio (i.e. those whose contents have flipped) are marked or otherwise identified as “weak” (step 114).

摘要翻译： 一种用于测试静态随机存取存储器（SRAM）阵列以存在弱缺陷的方法和装置。 首先将0/1比率写入存储器阵列（步骤100），然后将位线BL和BLB预充电并均衡到阈值检测电压（步骤102）。 阈值检测电压根据单元的0/1比率编程，以便考虑特定的单元标准和/或特性。 接下来，与阵列中的所有单元相关联的字线基本上同时被启用（步骤104），然后将位线一起短接（步骤106），字线被禁用（步骤108）并且位线被释放 （步骤110）。 按照这些步骤，读取SRAM阵列的内容并将其与原始的0/1比率进行比较（步骤112）。 内容不符合原始0/1比例（即内容已经翻转的内容）的单元格被标记或以其他方式标识为“弱”（步骤114）。

公开(公告)号：US07200057B2

公开(公告)日：2007-04-03

申请号：US10548340

申请日：2004-03-03

申请人： Jose De Jesus Pineda De Gyvez ,  Manoj Sachdev ,  Andrei Pavlov

发明人： Jose De Jesus Pineda De Gyvez ,  Manoj Sachdev ,  Andrei Pavlov

IPC分类号： G11C7/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C2029/5006

摘要： A method and apparatus for testing a static random access memory (SRAM) array for the presence of weak defects. A 0/1 ratio is first written to the memory array (step 100), following which the bit lines BL and BLB are pre-charged and equalized to a threshold detection voltage (step 102). The threshold detection voltage is programmed according to the 0/1 ratio of cells, so as to take into account specific cell criterion and/or characteristics. Next, the word lines associated with all of the cells in the array are enabled substantially simultaneously (step 104), the bit lines are then shorted together (step 106), the word lines are disabled (step 108) and the bit lines are released (step 110). Following these steps, the contents of the SRAM array are read and compared against the original 0/1 ratio (step 112). 10 Any cells whose contents do not match the original 0/1 ratio (i.e. those whose contents have flipped) are marked or otherwise identified as “weak” (step 114).

摘要翻译： 一种用于测试静态随机存取存储器（SRAM）阵列以存在弱缺陷的方法和装置。 首先将0/1比率写入存储器阵列（步骤100），然后将位线BL和BLB预充电并均衡到阈值检测电压（步骤102）。 阈值检测电压根据单元的0/1比率编程，以便考虑特定的单元标准和/或特性。 接下来，与阵列中的所有单元相关联的字线基本上同时被启用（步骤104），然后将位线一起短接（步骤106），字线被禁用（步骤108）并且位线被释放 （步骤110）。 按照这些步骤，读取SRAM阵列的内容并将其与原始的0/1比率进行比较（步骤112）。 内容不符合原始0/1比例（即内容已经翻转的内容）的单元格被标记或以其他方式标识为“弱”（步骤114）。

公开(公告)号：US09542995B2

公开(公告)日：2017-01-10

申请号：US14470866

申请日：2014-08-27

申请人： Manoj Sachdev ,  Jaspal Singh Shah

发明人： Manoj Sachdev ,  Jaspal Singh Shah

IPC分类号： G11C11/419

CPC分类号： G11C11/419

摘要： Sense amplifier configurations for memories are described. In these configurations, the differential inputs are boosted proportional to the respective bitline voltage enabling a low-voltage, reliable, faster sense amplifier operation. Disclosed sense amplifiers are also capable of compensating the threshold mismatch between the sensing transistors.

摘要翻译： 描述用于存储器的感测放大器配置。 在这些配置中，差分输入与相应的位线电压成正比，从而能够实现低电压，可靠，更快的读出放大器操作。 公开的读出放大器还能够补偿感测晶体管之间的阈值失配。

公开(公告)号：US07643329B2

公开(公告)日：2010-01-05

申请号：US11621679

申请日：2007-01-10

申请人： Manoj Sachdev ,  Mohammad Sharifkhani

发明人： Manoj Sachdev ,  Mohammad Sharifkhani

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C11/413

摘要： An asymmetric Static Random Access Memory (SRAM) cell is provided. The SRAM cell comprises first and second storage nodes, drive transistors and access transistors. The first and second storage nodes are configured to store complementary voltages. The drive transistors are configured to selectively couple each of the first and second storage nodes to corresponding high and low voltage power supplies, and maintain a first logic state through a feedback loop. The access transistors are configured to selectively couple each of the first and second storage nodes to corresponding first and second bit-lines and maintain a second logic state through relative transistor leakage currents. A method for reading from and writing to the SRAM cell are also provided.

摘要翻译： 提供了非对称静态随机存取存储器（SRAM）单元。 SRAM单元包括第一和第二存储节点，驱动晶体管和存取晶体管。 第一和第二存储节点被配置为存储互补电压。 驱动晶体管被配置为选择性地将第一和第二存储节点中的每一个耦合到相应的高电压和低电压电源，并且通过反馈回路保持第一逻辑状态。 存取晶体管被配置为选择性地将第一和第二存储节点中的每一个耦合到相应的第一和第二位线，并通过相对晶体管漏电流维持第二逻辑状态。 还提供了用于从SRAM单元读取和写入SRAM单元的方法。

公开(公告)号：US5831463A

公开(公告)日：1998-11-03

申请号：US696311

申请日：1996-08-13

申请人： Manoj Sachdev

发明人： Manoj Sachdev

IPC分类号： G01R31/30 ,  H03K3/037 ,  H03K19/173 ,  H03K3/3562

CPC分类号： G01R31/3008 ,  G01R31/3004 ,  H03K3/0372

摘要： A master-slave flip-flop has master and slave latches cascaded between an input and an output. Each latch has two inverters directly connected to one another head to tail. The latches are coupled via a buffer and a clock controlled pass gate. This architecture reduces the number of pass gates and clock lines, improves hold time and enhances I.sub.DDQ -testability with respect to known flip-flops.

摘要翻译： 主从触发器具有在输入和输出之间级联的主从锁存器。 每个锁存器都有两个逆变器直接连接到另一个头尾。 锁存器通过缓冲器和时钟控制的通过门耦合。 该架构减少了通过门和时钟线的数量，改善了保持时间，并提高了与已知触发器的IDDQ可测试性。

公开(公告)号：US5751141A

公开(公告)日：1998-05-12

申请号：US532338

申请日：1995-09-21

申请人： Manoj Sachdev ,  Botjo Atzema

发明人： Manoj Sachdev ,  Botjo Atzema

IPC分类号： G01R31/316 ,  G01R31/28 ,  G01R31/30 ,  G05F3/24 ,  H01L21/822 ,  H01L27/04 ,  H03M1/10 ,  H03M1/36 ,  G05F3/04 ,  H01H31/02

CPC分类号： H03M1/108 ,  G01R31/3004 ,  G01R31/3008 ,  H03M1/36

摘要： A bias generator is tested in an I.sub.DDQ -scheme by applying each respective one of the bias voltages to a respective PFET that is individually gated by a respective NFET. This permits measuring the quiescent currents. Any deviation in the bias voltages is translated into a deviation of the quiescent current.

摘要翻译： 通过将各自的偏置电压施加到由相应的NFET分别门控的相应PFET，以IDDQ方案测试偏置发生器。 这允许测量静态电流。 偏置电压的任何偏差被转换为静态电流的偏差。

公开(公告)号：US20240144887A1

公开(公告)日：2024-05-02

申请号：US18385570

申请日：2023-10-31

申请人： Sheida GOHARDEHI ,  Manoj Sachdev

发明人： Sheida GOHARDEHI ,  Manoj Sachdev

IPC分类号： G09G3/3275

CPC分类号： G09G3/3275 ,  G09G2300/0852 ,  G09G2310/08 ,  G09G2330/023

摘要： The disclosure is directed at energy and/or power recycling techniques for use with portable displays in order to extend battery life for portable displays.

公开(公告)号：US20160203856A1

公开(公告)日：2016-07-14

申请号：US14470866

申请日：2014-08-27

申请人： Manoj Sachdev ,  Jaspal Singh Shah

发明人： Manoj Sachdev ,  Jaspal Singh Shah

IPC分类号： G11C11/419

CPC分类号： G11C11/419

摘要： Sense amplifier configurations for memories are described. In these configurations, the differential inputs are boosted proportional to the respective bitline voltage enabling a low-voltage, reliable, faster sense amplifier operation. Disclosed sense amplifiers are also capable of compensating the threshold mismatch between the sensing transistors.

摘要翻译： 描述用于存储器的感测放大器配置。 在这些配置中，差分输入与相应的位线电压成正比，从而能够实现低电压，可靠，更快的读出放大器操作。 公开的读出放大器还能够补偿感测晶体管之间的阈值失配。

公开(公告)号：US08488403B2

公开(公告)日：2013-07-16

申请号：US12757033

申请日：2010-04-08

申请人： Manoj Sachdev ,  Mohammad Sharifkhani ,  Jaspal Singh Shah ,  David Rennie

发明人： Manoj Sachdev ,  Mohammad Sharifkhani ,  Jaspal Singh Shah ,  David Rennie

IPC分类号： G11C7/02

CPC分类号： G11C7/062 ,  G11C2207/063 ,  G11C2207/104

摘要： An offset cancellation scheme for sense amplification is described. The scheme consists of group of transistors which are selectively coupled to high and low voltage levels via multi-phase timing. This results in a voltage level on sensing nodes of interest which are a function of transistor mismatch. The resulting voltage levels act to compensates for the transistor mismatch, thereby improving the reliability of the sense amplifier in the presence of process non-idealities. The offset cancellation scheme is applicable to numerous types of sense amplifiers, amplifiers, and comparators.

摘要翻译： 描述了用于感测放大的偏移消除方案。 该方案由通过多相定时选择性地耦合到高电压和低电压电平的晶体管组成。 这导致感兴趣的感测节点上的电压电平，其是晶体管不匹配的函数。 所产生的电压电平用于补偿晶体管失配，从而在存在工艺非理想性的情况下提高读出放大器的可靠性。 偏移消除方案适用于许多类型的读出放大器，放大器和比较器。

公开(公告)号：US08072797B2

公开(公告)日：2011-12-06

申请号：US12494908

申请日：2009-06-30

申请人： Manoj Sachdev ,  David Rennie

发明人： Manoj Sachdev ,  David Rennie

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： A Static Random Access Memory (SRAM) cell without dedicated access transistors is described. The SRAM cell comprises a plurality of transistors configured to provide at least a pair of storage nodes for storing complementary logic values represented by corresponding voltages. The transistors comprise at least one bitline transistor, at least on wordline transistor and at least two supply transistors. The bitline transistor is configured to selectively couple one of the storage nodes to at least one corresponding bitline, the bitline for being shared by SRAM cells in one of a common row or column. The wordline transistor is configured to selectively couple another of the storage nodes to at least one corresponding wordline, the wordline for being shared by SRAM cells in the other of the common row or column. The supply transistors are configured to selectively couple corresponding ones of the storage nodes to a supply voltage.

摘要翻译： 描述了没有专用存取晶体管的静态随机存取存储器（SRAM）单元。 SRAM单元包括多个晶体管，其被配置为提供至少一对存储节点，用于存储由对应电压表示的互补逻辑值。 晶体管至少在字线晶体管和至少两个电源晶体管上包括至少一个位线晶体管。 位线晶体管被配置为选择性地将存储节点之一耦合到至少一个相应的位线，该位线用于由公共行或列之一中的SRAM单元共享的位线。 字线晶体管被配置为选择性地将另一个存储节点耦合到至少一个相应的字线，该字线由公共行或列中的另一个中的SRAM单元共享。 电源晶体管被配置为选择性地将相应的存储节点耦合到电源电压。