公开(公告)号：US20170287929A1

公开(公告)日：2017-10-05

申请号：US15514239

申请日：2014-09-26

申请人： Sunggil KIM ,  Phil Ouk NAM ,  Gukhyon YON ,  Sunghae LEE ,  Woojin JANG ,  Dongchul YOO ,  Hunhyeong LIM ,  Junggeun JEE ,  Kihyun HWANG

发明人： Sunggil KIM ,  Phil Ouk NAM ,  Gukhyon YON ,  Sunghae LEE ,  Woojin JANG ,  Dongchul YOO ,  Hunhyeong LIM ,  Junggeun JEE ,  Kihyun HWANG

IPC分类号： H01L27/11582 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L27/1157 ,  H01L29/10

CPC分类号： H01L27/11582 ,  H01L21/0206 ,  H01L21/31116 ,  H01L27/115 ,  H01L27/1157 ,  H01L28/00 ,  H01L29/1037 ,  H01L29/40117

摘要： The inventive concepts provide semiconductor memory devices and methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel filling a channel hole vertically penetrating the plurality of gates, and a memory layer vertically extending on an inner sidewall of the channel. The vertical channel may include a lower channel filling a lower region of the channel hole and electrically connected to the substrate, and an upper channel filling an upper region of the channel hole and contacting the lower channel. The upper channel may extend along the memory layer and the lower channel in the upper region of the channel hole and may have a uniform thickness.

公开(公告)号：US20130095622A1

公开(公告)日：2013-04-18

申请号：US13567320

申请日：2012-08-06

申请人： JUNGGEUN JEE ,  Woosung Lee

发明人： JUNGGEUN JEE ,  Woosung Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/7889

摘要： Methods of manufacturing a semiconductor device are provided. Patterns having a recess region defined therebetween are formed on a substrate, and then a silicon precursor having an organic ligand is provided on the substrate to absorb silicon on sidewalls and a bottom surface of the recess region to form a silicon monolayer on the patterns having the recess region defined therebetween. A silicon layer without void and cutting is formed on the silicon monolayer.

摘要翻译： 提供制造半导体器件的方法。 在衬底上形成具有凹陷区域的图案，然后在衬底上提供具有有机配体的硅前体，以吸收凹槽区域的侧壁和底表面上的硅，以在具有有机配体的图案上形成硅单层 凹陷区域。 在硅单层上形成无空隙和切割的硅层。

公开(公告)号：US10685972B2

公开(公告)日：2020-06-16

申请号：US15514239

申请日：2014-09-26

申请人： Sunggil Kim ,  Phil Ouk Nam ,  Gukhyon Yon ,  Sunghae Lee ,  Woojin Jang ,  Dongchul Yoo ,  Hunhyeong Lim ,  Junggeun Jee ,  Kihyun Hwang

发明人： Sunggil Kim ,  Phil Ouk Nam ,  Gukhyon Yon ,  Sunghae Lee ,  Woojin Jang ,  Dongchul Yoo ,  Hunhyeong Lim ,  Junggeun Jee ,  Kihyun Hwang

IPC分类号： H01L27/11582 ,  H01L27/11568 ,  H01L21/28 ,  H01L27/115 ,  H01L49/02 ,  H01L21/02 ,  H01L21/311 ,  H01L27/1157 ,  H01L29/10

摘要： The inventive concepts provide semiconductor memory devices and methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel filling a channel hole vertically penetrating the plurality of gates, and a memory layer vertically extending on an inner sidewall of the channel. The vertical channel may include a lower channel filling a lower region of the channel hole and electrically connected to the substrate, and an upper channel filling an upper region of the channel hole and contacting the lower channel. The upper channel may extend along the memory layer and the lower channel in the upper region of the channel hole and may have a uniform thickness.

公开(公告)号：US20150145020A1

公开(公告)日：2015-05-28

申请号：US14510532

申请日：2014-10-09

申请人： CHAEHO KIM ,  KIHYUN HWANG ,  DONGWOO KIM ,  WOONG LEE ,  JUNGGEUN JEE

发明人： CHAEHO KIM ,  KIHYUN HWANG ,  DONGWOO KIM ,  WOONG LEE ,  JUNGGEUN JEE

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A method of fabricating a three-dimensional (3D) semiconductor memory device is provided. Sacrificial layers and insulating layers are alternately and repeatedly stacked on a top surface of a substrate to form a thin layer structure. A channel structure penetrating the thin layer structure is formed to be in contact with the substrate. A trench penetrating the thin layer structure is formed. The sacrificial layers, the insulating layers and the substrate are exposed in the trench. A recess region formed in the substrate exposed by the trench. A semiconductor pattern filling is formed the recess region. The sacrificial layers exposed by the trench are replaced with gate patterns.

摘要翻译： 提供一种制造三维（3D）半导体存储器件的方法。 牺牲层和绝缘层交替重复堆叠在基板的顶表面上以形成薄层结构。 穿透薄层结构的沟道结构形成为与衬底接触。 形成穿透薄层结构的沟槽。 牺牲层，绝缘层和衬底暴露在沟槽中。 形成在衬底中的由沟槽暴露的凹陷区域。 半导体图案填充形成为凹部。 由沟槽暴露的牺牲层被栅极图案替代。

公开(公告)号：US08697519B2

公开(公告)日：2014-04-15

申请号：US13567320

申请日：2012-08-06

申请人： Junggeun Jee ,  Woosung Lee

发明人： Junggeun Jee ,  Woosung Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/7889

摘要： Methods of manufacturing a semiconductor device are provided. Patterns having a recess region defined therebetween are formed on a substrate, and then a silicon precursor having an organic ligand is provided on the substrate to absorb silicon on sidewalls and a bottom surface of the recess region to form a silicon monolayer on the patterns having the recess region defined therebetween. A silicon layer without void and cutting is formed on the silicon monolayer.

摘要翻译： 提供制造半导体器件的方法。 在衬底上形成具有凹陷区域的图案，然后在衬底上提供具有有机配体的硅前体，以吸收凹槽区域的侧壁和底表面上的硅，以在具有有机配体的图案上形成硅单层 凹陷区域。 在硅单层上形成无空隙和切割的硅层。