摘要:
The present invention relates to an automatic bit-changing screwdriver including a bit tip and a bit shaft assembly. The bit tip and the bit shaft assembly are pivotably connected. Guided by the bit shaft assembly, the bit tip may rotate relative to the bit shaft assembly and change the tip without requiring direct manual contact with the bit tip. Particularly, the screwdriver includes a handle, a bit tip, a shaft and a shaft sleeve. The bit tip includes two sizes/styles of tips at two ends respectively. The bit tip is pivotably coupled to the shaft. The shaft is fixedly coupled to the handle. The shaft sleeve surrounds the shaft. The shaft and shaft sleeve are slidingly coupled together. Outwards sliding of the shaft sleeve drives the bit tip to rotate within the shaft to achieve bit-changing. A deep groove is formed on a front end of the shaft. The bit tip is disposed in the deep groove. A middle section of the shaft has a guide groove. The shaft sleeve is connected to the guide groove by a connecting element disposed along the guide groove. A slide guide block is fixedly positioned on the shaft sleeve facing a side of the shaft having the deep groove. The shaft sleeve has a notch. The notch is formed in a middle section of the shaft sleeve. A spring element is connected to the shaft sleeve. The spring element moves within the notch. The automatic bit-changing screwdriver provides a solution to a technical problem that the state of the art combination screwdrivers are generally inconvenient to change bits.
摘要:
Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage.
摘要:
Embodiments of the present invention may provide accuracy enhancement techniques to improve ADC SNRs. For example, regular bit trials from a most significant bit (MSB) to predetermined less significant bit of a digital word and extra bit trials may be performed. The results of the regular and extra bit trials may be combined to generate a digital output signal. A residue error may be measured, and the digital output signal may be adjusted based on the measured residue error.
摘要:
Circuits and methods for implementing a residue amplifier are provided. In some embodiments, circuits for implementing a residue amplifier are provided, the circuits comprising: a first capacitor configured to be charged to an input voltage level and that discharges from the input voltage level to a reference voltage level; a comparator having a first input coupled to the first capacitor, a second input coupled to a reference voltage source, and an output that indicates when the charge on the first capacitor is above the reference voltage level; and a second capacitor configured to be charged to an output voltage based on the output of the comparator.
摘要:
Circuits and methods for implementing a residue amplifier are provided. In some embodiments, circuits for implementing a residue amplifier are provided, the circuits comprising: a first capacitor configured to be charged to an input voltage level and that discharges from the input voltage level to a reference voltage level; a comparator having a first input coupled to the first capacitor, a second input coupled to a reference voltage source, and an output that indicates when the charge on the first capacitor is above the reference voltage level; and a second capacitor configured to be charged to an output voltage based on the output of the comparator.
摘要:
Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage.
摘要:
Embodiments of the present invention may provide accuracy enhancement techniques to improve ADC SNRs. For example, regular bit trials from a most significant bit (MSB) to predetermined less significant bit of a digital word and extra bit trials may be performed. The results of the regular and extra bit trials may be combined to generate a digital output signal. A residue error may be measured, and the digital output signal may be adjusted based on the measured residue error.
摘要:
Embodiments of the present invention may provide an analog-to-digital converter (ADC) system. The ADC system may include an analog circuit to receive an input signal and a reference voltage, and to convert the input signal into a raw digital output. The analog circuit may include at least one sampling element to sample the input signal during a sampling phase and reused to connect to the reference voltage during a conversion phase, and an ADC output to output the raw digital output. The ADC system may also include a digital processor to receive the raw digital output and for each clock cycle, to digitally correct reference voltage errors in the analog-to-digital conversion.
摘要:
The present invention relates to an automatic bit-changing screwdriver including a bit tip and a bit shaft assembly. The bit tip and the bit shaft assembly are pivotably connected. Guided by the bit shaft assembly, the bit tip may rotate relative to the bit shaft assembly and change the tip without requiring direct manual contact with the bit tip. Particularly, the screwdriver includes a handle, a bit tip, a shaft and a shaft sleeve. The bit tip includes two sizes/styles of tips at two ends respectively. The bit tip is pivotably coupled to the shaft. The shaft is fixedly coupled to the handle. The shaft sleeve surrounds the shaft. The shaft and shaft sleeve are slidingly coupled together. Outwards sliding of the shaft sleeve drives the bit tip to rotate within the shaft to achieve bit-changing. A deep groove is formed on a front end of the shaft. The bit tip is disposed in the deep groove. A middle section of the shaft has a guide groove. The shaft sleeve is connected to the guide groove by a connecting element disposed along the guide groove. A slide guide block is fixedly positioned on the shaft sleeve facing a side of the shaft having the deep groove. The shaft sleeve has a notch. The notch is formed in a middle section of the shaft sleeve. A spring element is connected to the shaft sleeve. The spring element moves within the notch. The automatic bit-changing screwdriver provides a solution to a technical problem that the state of the art combination screwdrivers are generally inconvenient to change bits.
摘要:
An uncalibrated converter element in an analog-digital converter may be replaced with two or more smaller elements having an effective total net value that is equal to that of the uncalibrated converter element. In an exemplary case where the element is capacitor, one or more of these smaller capacitors may be independently calibrated by switching the smaller capacitor between two voltages, such as a reference voltage and ground, and then calculating a difference of corresponding digital output codes generated by the backend ADC with previously calibrated capacitors associated with lesser significant bits. The total capacitance of the uncalibrated capacitor may be apportioned between the smaller capacitors so that the individual maximum charge contribution of each smaller capacitor to the converter output together with any expected manufacturing variance does not exceed the aggregated contribution of the previously calibrated capacitors.