公开(公告)号：US20050230725A1

公开(公告)日：2005-10-20

申请号：US10828446

申请日：2004-04-20

Applicant: Sanjeev Aggarwal ,  K.R. Udayakumar ,  Scott Summerfelt

Inventor： Sanjeev Aggarwal ,  K.R. Udayakumar ,  Scott Summerfelt

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/8246 ,  H01L27/115

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/57 ,  H01L28/65 ,  H01L28/75

Abstract: The present invention provides a ferroelectric capacitor, a method for manufacture therefor, and a ferroelectric random access memory (FeRAM) device. The ferroelectric capacitor (100), among other elements, may include a first electrode layer (162) located over a substrate (110), wherein the first electrode layer (162) includes iridium, and an oxide electrode template (164) located over the first electrode layer (162). The ferroelectric capacitor (100) may further include a ferroelectric dielectric layer (165) located over the oxide electrode template (164), and a second electrode layer (170) located over the ferroelectric dielectric layer (165).

Abstract translation: 本发明提供一种铁电电容器及其制造方法以及铁电随机存取存储器（FeRAM）器件。 铁电电容器（100）以及其他元件可以包括位于基板（110）上方的第一电极层（162），其中第一电极层（162）包括铱，以及氧化物电极模板（164） 第一电极层（162）。 铁电电容器（100）还可以包括位于氧化物电极模板（164）上方的铁电介质层（165）和位于铁电介质层（165）上方的第二电极层（170）。

公开(公告)号：US20050112898A1

公开(公告)日：2005-05-26

申请号：US10721932

申请日：2003-11-25

Applicant: K.R. Udayakumar ,  Ted Moise ,  Scott Summerfelt ,  Martin Albrecht ,  William Dostalik ,  Francis Celii

Inventor： K.R. Udayakumar ,  Ted Moise ,  Scott Summerfelt ,  Martin Albrecht ,  William Dostalik ,  Francis Celii

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/316 ,  H01L21/768 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/31116 ,  H01L21/31616 ,  H01L21/76895 ,  H01L28/55

Abstract: The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130 located thereunder, and then etching an opening 150, 155, in the substrate 140 using an etchant comprising carbon oxide, a fluorocarbon, an etch rate modulator, and an inert carrier gas, wherein a flow rate of the carbon oxide is greater than about 80 sccm and the etchant is selective to the aluminum oxide etch stop layer 130. The aluminum oxide etch stop layer may also be used in the back-end of advanced CMOS processes as a via etch stop layer.

Abstract translation: 本发明提供了蚀刻基板的方法，集成电路的形成方法，使用该方法形成的集成电路和集成电路。 除了其他步骤之外，用于蚀刻衬底的方法包括提供具有位于其下方的氧化铝蚀刻停止层130的衬底140，然后使用包含碳氧化物，碳氟化合物的蚀刻剂在衬底140中蚀刻开口150,155， 蚀刻速率调制器和惰性载气，其中碳氧化物的流速大于约80sccm，并且蚀刻剂对氧化铝蚀刻停止层130是选择性的。 氧化铝蚀刻停止层也可用作先进CMOS工艺的后端作为通孔蚀刻停止层。

公开(公告)号：US20050145908A1

公开(公告)日：2005-07-07

申请号：US10749668

申请日：2003-12-30

Applicant: Theodore Moise ,  Scott Summerfelt ,  K.R. Udayakumar

Inventor： Theodore Moise ,  Scott Summerfelt ,  K.R. Udayakumar

IPC: H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H01L21/00 ,  H01L29/76

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55

Abstract: One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectic cores during cooling.

Abstract translation: 本发明的一个方面涉及一种制造集成电路的方法，包括在半导体衬底上形成铁电存储器单元的阵列，将衬底加热到​​铁电芯的居里温度附近的温度，并对衬底进行温度程序 ，由此当铁芯冷却至约室温时，铁电芯上的热诱导应力使芯的开关极化增加至少约25％。 本发明的实施例包括在铁电芯上方和下方的膨胀横截面的金属填充通孔，其在冷却期间增加铁电芯上的热应力。

公开(公告)号：US20050012126A1

公开(公告)日：2005-01-20

申请号：US10620516

申请日：2003-07-16

Applicant: K. Udayakumar ,  Martin Albrecht ,  Theodore Moise ,  Scott Summerfelt ,  Sanjeev Aggarwal ,  Jeff Large

Inventor： K. Udayakumar ,  Martin Albrecht ,  Theodore Moise ,  Scott Summerfelt ,  Sanjeev Aggarwal ,  Jeff Large

IPC: H01L21/02 ,  H01L23/00 ,  H01L29/06 ,  H01L21/00 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072

CPC classification number: H01L28/57 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices and fabrication methods are presented, in which a hydrogen barrier is provided above a ferroelectric capacitor to prevent degradation of the ferroelectric material during back-end manufacturing processes employing hydrogen. The hydrogen barrier comprises silicon rich silicon oxide or amorphous silicon, which can be used in combination with an aluminum oxide layer to inhibit diffusion of process-related hydrogen into the ferroelectric capacitor layer.

Abstract translation: 提出了半导体器件和制造方法，其中在铁电电容器上方设置氢气阻挡层，以防止在使用氢的后端制造工艺期间铁电材料的劣化。 氢势垒包括富硅氧化物或非晶硅，其可以与氧化铝层组合使用以抑制工艺相关氢扩散到铁电电容器层中。

公开(公告)号：US20120170350A1

公开(公告)日：2012-07-05

申请号：US13243875

申请日：2011-09-23

Applicant: Michael Patrick Clinton ,  Steven Craig Bartling ,  Scott Summerfelt ,  Hugh McAdams

Inventor： Michael Patrick Clinton ,  Steven Craig Bartling ,  Scott Summerfelt ,  Hugh McAdams

IPC: G11C11/22

CPC classification number: G11C11/1673 ,  G11C11/1677 ,  G11C11/22 ,  G11C29/12 ,  G11C29/30 ,  G11C2029/1202 ,  G11C2029/5002

Abstract: An FRAM device can comprise a sense amplifier, at least a first bitcell, a first control line, and a second control line. The first bitcell can have a bit line that connects to the sense amplifier via a first isolator and a complimentary bit line that connects to the sense amplifier via a second isolator that is different from the first isolator. The first control line can connect to and control the aforementioned first isolator. And the second control line can connect to and control the second isolator such that the second isolator is independently controlled with respect to the first isolator to facilitate testing the device.

Abstract translation: FRAM设备可以包括读出放大器，至少第一位单元，第一控制线和第二控制线。 第一位单元可以具有通过第一隔离器和与第一隔离器不同的第二隔离器连接到读出放大器的互补位线连接到读出放大器的位线。 第一控制线可以连接到并控制上述第一隔离器。 并且第二控制线可以连接到并控制第二隔离器，使得第二隔离器相对于第一隔离器被独立地控制，以便于测试设备。

公开(公告)号：US06819601B2

公开(公告)日：2004-11-16

申请号：US10454862

申请日：2003-06-05

Applicant: Jarrod Eliason ,  Bill Kraus ,  Hugh McAdams ,  Scott Summerfelt ,  Theodore S. Moise

Inventor： Jarrod Eliason ,  Bill Kraus ,  Hugh McAdams ,  Scott Summerfelt ,  Theodore S. Moise

IPC: G11C700

CPC classification number: G11C11/22

Abstract: A ferroelectric memory device is disclosed and comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one or more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereto for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and the reference voltage on the second bit line.

公开(公告)号：US06462931B1

公开(公告)日：2002-10-08

申请号：US08956407

申请日：1997-10-23

Applicant: Shaoping Tang ,  John Mark Anthony ,  Scott Summerfelt

Inventor： Shaoping Tang ,  John Mark Anthony ,  Scott Summerfelt

IPC: H01G4008

CPC classification number: H01L27/11502 ,  H01L27/10814 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75

Abstract: A capacitor (100) with a high dielectric constant oxide dielectric (102) plus Ir- or Ir and Rh bond over the oxygen site in Barium strontium titanate (BST) dielectric to achieve the high Schottky barrier, and very thin layers of Ir or Rh with conductive oxide backing layers (106, 116) provide oxygen depletion deterrence. Rh-containing capacitor plates (104, 114) yielding high Schottky barrier interfaces.

Abstract translation: 具有高介电常数氧化物电介质（102）的电容器（102）加上在锶钛酸锶（BST）电介质中的氧位置上的Ir或Ir和Rh键，以实现高肖特基势垒，以及非常薄的Ir或Rh 具有导电氧化物背衬层（106,116）提供氧耗尽威慑。 含Rh的电容器板（104,114）产生高肖特基势垒界面。

公开(公告)号：US20120170351A1

公开(公告)日：2012-07-05

申请号：US13243911

申请日：2011-09-23

Applicant: Michael Patrick Clinton ,  Steven Craig Bartling ,  Scott Summerfelt ,  Hugh McAdams

Inventor： Michael Patrick Clinton ,  Steven Craig Bartling ,  Scott Summerfelt ,  Hugh McAdams

IPC: G11C11/22

CPC classification number: G11C11/1673 ,  G11C11/1677

Abstract: An FRAM device can comprise a sense amplifier and at least a first bitcell. The first bitcell can have a bit line and a complimentary bit line that connects to the sense amplifier. A first precharge circuit responds to a first control signal during a test mode of operation to precharge the bit line with respect to a first voltage while a second precharge circuit responds to a second control signal (that is different from the first control signal) during the test mode of operation to precharge the complimentary bit line with respect to a test voltage that is different than the first voltage (such as, but not limited to, a test voltage of choice such as a voltage that is greater than ground but less than the first voltage).

Abstract translation: FRAM设备可以包括读出放大器和至少第一位单元。 第一位单元可以具有连接到读出放大器的位线和互补位线。 第一预充电电路在测试操作模式期间响应第一控制信号，以相对于第一电压对位线预充电，而在第二预充电电路期间第二预充电电路响应第二控制信号（与第一控制信号不同） 测试操作模式相对于不同于第一电压的测试电压（例如但不限于，例如大于地电压但小于第一电压的选择的测试电压）预充电补充位线 第一电压）。

公开(公告)号：US20050205906A1

公开(公告)日：2005-09-22

申请号：US10803445

申请日：2004-03-18

Applicant: K. Udayakumar ,  Theodore Moise ,  Scott Summerfelt

Inventor： K. Udayakumar ,  Theodore Moise ,  Scott Summerfelt

IPC: H01L27/105 ,  H01L21/02 ,  H01L21/8246 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L27/11507 ,  H01L28/57

Abstract: Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.

Abstract translation: 提供氢屏障和制造方法用于在半导体器件（102）中保护铁电电容器（C LIMIT）免受氢扩散，其中氮化的氧化铝（N-AlOx）形成在铁电电容器（C < 在氮化的氧化铝（N-AlOx）上形成一个或多个氮化硅层（112,117）。 还提供了氢屏障，其中在铁电电容器（CFE）上形成氧化铝（AlOx，N-AlOx），其上形成有两个或更多个氮化硅层（112,117） 氧化铝（AlOx，N-AlOx），其中第二氮化硅层（112）包括低硅氢SiN材料。

公开(公告)号：US20050054122A1

公开(公告)日：2005-03-10

申请号：US10968721

申请日：2004-10-19

Applicant: Francis Celii ,  Scott Summerfelt ,  Mahesh Thakre

Inventor： Francis Celii ,  Scott Summerfelt ,  Mahesh Thakre

IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/311 ,  H01L21/316 ,  H01L21/3213 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L21/00

CPC classification number: H01L27/11502 ,  H01L21/31122 ,  H01L21/31691 ,  H01L21/32139 ,  H01L27/11507 ,  H01L28/55

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl3 etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF3 to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a “shorting out” of the resulting FeRAM capacitor.

Abstract translation: 本发明涉及形成FeRAM集成电路的方法，其包括执行电容器堆叠蚀刻以限定FeRAM电容器。 该方法包括用提供相对于硬掩模的实质选择性的高温BCl3蚀刻来蚀刻PZT铁电层。 或者，PZT铁电层是使用诸如CHF 3的低温氟成分蚀刻化学品进行蚀刻，以提供非垂直PZT侧壁轮廓。 这种轮廓防止与随后的底部电极层蚀刻相关联的导电材料沉积在PZT侧壁上，从而防止所得FeRAM电容器的泄漏或“短路”。