公开(公告)号：US07512087B2

公开(公告)日：2009-03-31

申请号：US09969916

申请日：2001-10-02

申请人： Munehiro Yoshikawa ,  Kenichi Sakusabe

发明人： Munehiro Yoshikawa ,  Kenichi Sakusabe

IPC分类号： H04W4/00

CPC分类号： H04W48/00 ,  H04H20/02 ,  H04H20/63 ,  H04L12/2838 ,  H04L12/5692 ,  H04N17/00 ,  H04N21/4135 ,  H04N21/43615 ,  H04N21/44209 ,  H04N21/4425 ,  H04N21/4782 ,  H04N21/4786 ,  H04W88/06

摘要： A communication system, method and apparatus which can maintain favorable communication quality without imposing much burden upon a user. A plurality of communication networks are formed between first and second communication apparatus. Upon starting communication between the first and second apparatus, communication quality of the communication networks is measured using at least one of the communication apparatus. One of the communication apparatus is selected for communication based on a result of the measurement. The first and second apparatus may be a base apparatus and a portable terminal apparatus, respectively, for use in the home, in which the base apparatus receives a television broadcast and transmits a selected television program of the broadcast to the terminal apparatus for display thereon. The communication networks may include a radio network and a wireline network. The terminal apparatus may also be adapted to access the Internet via the base apparatus.

公开(公告)号：US07417960B2

公开(公告)日：2008-08-26

申请号：US11008546

申请日：2004-12-09

申请人： Kenichi Sakusabe

发明人： Kenichi Sakusabe

IPC分类号： H04L5/16

CPC分类号： H04L1/1664 ,  H04L5/16 ,  H04L29/06 ,  H04L69/324

摘要： A communication apparatus for performing half duplex communications has: a memory circuit storing transmission data; a transmission processing circuit generating a transmission frame; a transmission/reception processing circuit outputting as a transmission signal the transmission frame generated by the transmission processing circuit and generating a reception frame by receiving a transmission signal; and a transmission/reception managing circuit making the transmission processing circuit generate a transmission frame containing the transmission data in the confirmation response and supply the transmission frame to the transmission/reception processing circuit if a confirmation response to the reception of the transmission signal at the transmission/reception processing circuit is to be issued and if the transmission data is stored in the memory circuit.

摘要翻译： 一种用于执行半双工通信的通信装置具有：存储发送数据的存储电路; 发送处理电路，生成发送帧; 发送/接收处理电路，作为发送信号输出由发送处理电路生成的发送帧，并通过接收发送信号生成接收帧; 以及发送/接收管理电路，使得发送处理电路在确认响应中生成包含发送数据的发送帧，并且在发送时向发送/接收处理电路发送对发送信号的接收的确认响应 /接收处理电路，并且发送数据被存储在存储器电路中。

公开(公告)号：US20070067524A1

公开(公告)日：2007-03-22

申请号：US11508838

申请日：2006-08-24

申请人： Masaya Mouri ,  Kenichi Sakusabe

发明人： Masaya Mouri ,  Kenichi Sakusabe

IPC分类号： G06F13/42

CPC分类号： H04L65/4076 ,  H04L12/2803 ,  H04L12/2836 ,  H04L29/06027 ,  H04L65/602 ,  H04L65/80 ,  H04L69/14 ,  H04L2012/2841 ,  H04L2012/2845 ,  H04L2012/2849 ,  Y02D50/30

摘要： A system for transmitting and receiving image and audio data that is information on any of image and audio has a transmission apparatus and a reception apparatus. The transmission apparatus transmits the image and audio data using a multi-channel communication system and includes a first protocol conversion device. The reception apparatus receives the image and audio data using the multi-channel communication system and includes a second protocol conversion device. The transmission apparatus performs data conversion processing on the image and audio data by the first protocol conversion device using a protocol to produce parallel image and audio data, and transmits it to the reception apparatus using the multi-channel communication system. The reception apparatus receives the parallel data to perform data conversion processing on the parallel data using the protocol by the second protocol conversion device to return to the image and audio data.

摘要翻译： 用于发送和接收作为关于图像和音频中的任一个的信息的图像和音频数据的系统具有发送装置和接收装置。 发送装置使用多信道通信系统发送图像和音频数据，并且包括第一协议转换装置。 接收装置使用多声道通信系统接收图像和音频数据，并且包括第二协议转换装置。 发送装置利用第一协议转换装置对图像和音频数据进行数据转换处理，使用协议产生并行图像和音频数据，并使用多信道通信系统将其发送到接收装置。 接收装置接收并行数据，使用第二协议转换装置的协议对并行数据执行数据转换处理，以返回图像和音频数据。

公开(公告)号：US07933949B2

公开(公告)日：2011-04-26

申请号：US12113431

申请日：2008-05-01

申请人： Hideki Yoshida ,  Jin Sato ,  Kazuyuki Ikeda ,  Takashi Norizuki ,  Kenichi Sakusabe ,  Daisuke Kawaguchi ,  Munehiro Yoshikawa

发明人： Hideki Yoshida ,  Jin Sato ,  Kazuyuki Ikeda ,  Takashi Norizuki ,  Kenichi Sakusabe ,  Daisuke Kawaguchi ,  Munehiro Yoshikawa

IPC分类号： G06F15/16

CPC分类号： H04N21/4307 ,  H04N5/04 ,  H04N5/38 ,  H04N5/4401 ,  H04N21/23406 ,  H04N21/44004 ,  H04N21/478

摘要： A data processing apparatus constitutes a low-cost audio/video data transmission and reception system. A reception buffer monitoring circuit 21 monitors the size of receiver data being accumulated in a reception buffer 6. When the size of accumulated data is found to become higher than a high threshold, the circuit 21 causes a reception clock generation circuit 8 to generate a reception clock with a higher frequency. When the accumulated data size becomes lower than a low threshold, the reception clock is generated with a lower frequency. Based on the reception clock fed from the reception clock generation circuit 8, an audio/video decoder 7 decodes the audio/video data coming from the reception buffer 6. The data processing apparatus applies advantageously to a television transmission and reception system for transmitting and receiving TV broadcast signals.

摘要翻译： 数据处理装置构成低成本音频/视频数据发送和接收系统。 接收缓冲器监视电路21监视在接收缓冲器6中累积的接收机数据的大小。当发现累加数据的大小变得高于高阈值时，电路21使接收时钟产生电路8产生接收 时钟频率较高。 当累积的数据大小变得低于低阈值时，以较低的频率生成接收时钟。 基于从接收时钟发生电路8馈送的接收时钟，音频/视频解码器7解码来自接收缓冲器6的音频/视频数据。数据处理装置有利地应用于用于发送和接收的电视发送和接收系统 电视广播信号。

公开(公告)号：US20080259213A1

公开(公告)日：2008-10-23

申请号：US12113431

申请日：2008-05-01

申请人： Hideki Yoshida ,  Jin Sato ,  Kazuyuki Ikeda ,  Takashi Norizuki ,  Kenichi Sakusabe ,  Daisuke Kawaguchi ,  Munehiro Yoshikawa

发明人： Hideki Yoshida ,  Jin Sato ,  Kazuyuki Ikeda ,  Takashi Norizuki ,  Kenichi Sakusabe ,  Daisuke Kawaguchi ,  Munehiro Yoshikawa

IPC分类号： H04N5/06 ,  H04N7/26

CPC分类号： H04N21/4307 ,  H04N5/04 ,  H04N5/38 ,  H04N5/4401 ,  H04N21/23406 ,  H04N21/44004 ,  H04N21/478

摘要： A data processing apparatus constituting a low-cost audio/video data transmission and reception system is disclosed. A reception buffer monitoring circuit 21 monitors the size of receiver data being accumulated in a reception buffer 6. When the size of accumulated data is found to become higher than a high threshold, the circuit 21 causes a reception clock generation circuit 8 to generate a reception clock with a higher frequency. When the accumulated data size becomes lower than a low threshold, the reception clock is generated with a lower frequency. Based on the reception clock fed from the reception clock generation circuit 8, an audio/video decoder 7 decodes the audio/video data coming from the reception buffer 6. This invention applies advantageously to a television transmission and reception system for transmitting and receiving TV broadcast signals.

摘要翻译： 公开了构成低成本音频/视频数据发送和接收系统的数据处理装置。 接收缓冲器监视电路21监视在接收缓冲器6中积累的接收机数据的大小。 当发现累加数据的大小变得高于高阈值时，电路21使接收时钟产生电路8产生具有较高频率的接收时钟。 当累积的数据大小变得低于低阈值时，以较低的频率生成接收时钟。 基于从接收时钟发生电路8馈送的接收时钟，音频/视频解码器7解码来自接收缓冲器6的音频/视频数据。 本发明有利地适用于用于发送和接收TV广播信号的电视发射和接收系统。

公开(公告)号：US07987488B2

公开(公告)日：2011-07-26

申请号：US11508838

申请日：2006-08-24

申请人： Masaya Mouri ,  Kenichi Sakusabe

发明人： Masaya Mouri ,  Kenichi Sakusabe

IPC分类号： H04N7/18 ,  H04N7/173 ,  G06F9/32 ,  G06F15/16 ,  G06F13/00 ,  G06F13/362 ,  H03K17/00 ,  H04L12/42 ,  H04L12/403 ,  H04J3/04

CPC分类号： H04L65/4076 ,  H04L12/2803 ,  H04L12/2836 ,  H04L29/06027 ,  H04L65/602 ,  H04L65/80 ,  H04L69/14 ,  H04L2012/2841 ,  H04L2012/2845 ,  H04L2012/2849 ,  Y02D50/30

摘要： A system for transmitting and receiving image and audio data that is information on any of image and audio has a transmission apparatus and a reception apparatus. The transmission apparatus transmits the image and audio data using a multi-channel communication system and includes a first protocol conversion device. The reception apparatus receives the image and audio data using the multi-channel communication system and includes a second protocol conversion device. The transmission apparatus performs data conversion processing on the image and audio data by the first protocol conversion device using a protocol to produce parallel image and audio data, and transmits it to the reception apparatus using the multi-channel communication system. The reception apparatus receives the parallel data to perform data conversion processing on the parallel data using the protocol by the second protocol conversion device to return to the image and audio data.

摘要翻译： 用于发送和接收作为关于图像和音频中的任一个的信息的图像和音频数据的系统具有发送装置和接收装置。 发送装置使用多信道通信系统发送图像和音频数据，并且包括第一协议转换装置。 接收装置使用多声道通信系统接收图像和音频数据，并且包括第二协议转换装置。 发送装置利用第一协议转换装置对图像和音频数据进行数据转换处理，使用协议产生并行图像和音频数据，并使用多信道通信系统将其发送到接收装置。 接收装置接收并行数据，使用第二协议转换装置的协议对并行数据执行数据转换处理，以返回图像和音频数据。

公开(公告)号：US6121840A

公开(公告)日：2000-09-19

申请号：US997013

申请日：1997-12-23

申请人： Kenichi Sakusabe

发明人： Kenichi Sakusabe

IPC分类号： H03F1/22 ,  H03F1/56 ,  H03F3/193 ,  H03F3/16 ,  H03F3/191

CPC分类号： H03F1/226 ,  H03F1/565 ,  H03F3/1935 ,  H03F2200/372

摘要： Input matching is achieved for a high-frequency range having a center frequency of 0.8 GHz by a capacitor and a coil in an input matching circuit, and input matching is achieved for a high-frequency range having a center frequency of 1.9 GHz by another coil in the input matching circuit. Output matching is achieved for a high-frequency range having a center frequency of 0.8 GHz by a capacitor and a coil in an output matching circuit, and output matching is achieved for a high-frequency range having a center frequency of 1.9 GHz by another coil in the output matching circuit.

摘要翻译： 通过电容器和输入匹配电路中的线圈对具有0.8GHz中心频率的高频范围实现输入匹配，并且通过另一个线圈实现具有1.9GHz中心频率的高频范围的输入匹配 在输入匹配电路中。 通过电容器和输出匹配电路中的线圈对具有0.8GHz中心频率的高频范围实现输出匹配，并且通过另一线圈实现具有1.9GHz中心频率的高频范围的输出匹配 在输出匹配电路中。

公开(公告)号：US5789963A

公开(公告)日：1998-08-04

申请号：US825961

申请日：1997-04-04

申请人： Kenichi Sakusabe

发明人： Kenichi Sakusabe

IPC分类号： H03D7/00 ,  H03D7/12 ,  H03D9/06 ,  H03D7/16 ,  H04B1/28

CPC分类号： H03D9/0675 ,  H03D7/125

摘要： A low power consumption mixing circuit and process comprise first and second field effect transistors "FETs." The first and second FETs each have at least a control electrode and a drive electrode. The drive electrodes of the first and second FETs are coupled together by a capacitor. An AC signal is supplied to the control electrode of the first FET through a first matching circuit, and the first FET amplifies the AC signal. The capacitor removes the DC component from the amplified AC signal that appears at the drive electrode of the first FET. The amplified AC signal, which is free from the DC component, is provided to the drive electrode of the second FET. A second AC signal is supplied to the control electrode of the second FET by another matching circuit. The second FET mixes the first and second AC signals that are supplied to the drive electrode of the second FET. This mixed signal is then provided through an output matching circuit as a mixed output signal. A supply voltage is provided at the drive electrode of the first FET but no supply voltage is provided at the drive electrode of the second FET. Instead, a negative bias voltage is applied at the control electrode of the second FET which results in the DC current in the drive electrode of the second FET being in a saturation range which thereby provides improved mixing at the drive electrode and improved inter-terminal isolation.

摘要翻译： 低功耗混合电路和工艺包括第一和第二场效应晶体管“FET”。 第一和第二FET各自至少具有控制电极和驱动电极。 第一和第二FET的驱动电极通过电容器耦合在一起。 AC信号通过第一匹配电路提供给第一FET的控制电极，第一FET放大AC信号。 电容器从出现在第一FET的驱动电极处的放大的AC信号中去除DC分量。 没有DC分量的放大的AC信号被提供给第二FET的驱动电极。 另一匹配电路将第二AC信号提供给第二FET的控制电极。 第二FET混合提供给第二FET的驱动电极的第一和第二AC信号。 然后通过输出匹配电路将混合信号作为混合输出信号提供。 在第一FET的驱动电极处提供电源电压，但是在第二FET的驱动电极处没有电源电压。 相反，在第二FET的控制电极处施加负偏置电压，这导致第二FET的驱动电极中的直流电流处于饱和范围，从而在驱动电极处提供改进的混合并改善了端子间隔离 。

公开(公告)号：US07389318B2

公开(公告)日：2008-06-17

申请号：US10432881

申请日：2001-11-28

申请人： Hideki Yoshida ,  Jin Sato ,  Kazuyuki Ikeda ,  Takashi Norizuki ,  Kenichi Sakusabe ,  Daisuke Kawaguchi ,  Munehiro Yoshikawa

发明人： Hideki Yoshida ,  Jin Sato ,  Kazuyuki Ikeda ,  Takashi Norizuki ,  Kenichi Sakusabe ,  Daisuke Kawaguchi ,  Munehiro Yoshikawa

IPC分类号： G06F15/16

CPC分类号： H04N21/4307 ,  H04N5/04 ,  H04N5/38 ,  H04N5/4401 ,  H04N21/23406 ,  H04N21/44004 ,  H04N21/478

摘要： A data processing apparatus constituting a low-cost audio/video data transmission and reception system is disclosed. A reception buffer monitoring circuit 21 monitors the size of receiver data being accumulated in a reception buffer 6. When the size of accumulated data is found to become higher than a high threshold, the circuit 21 causes a reception clock generation circuit 8 to generate a reception clock with a higher frequency. When the accumulated data size becomes lower than a low threshold, the reception clock is generated with a lower frequency. Based on the reception clock fed from the reception clock generation circuit 8, an audio/video decoder 7 decodes the audio/video data coming from the reception buffer 6. This invention applies advantageously to a television transmission and reception system for transmitting and receiving TV broadcast signals.

摘要翻译： 公开了构成低成本音频/视频数据发送和接收系统的数据处理装置。 接收缓冲器监视电路21监视在接收缓冲器6中积累的接收机数据的大小。 当发现累加数据的大小变得高于高阈值时，电路21使接收时钟产生电路8产生具有较高频率的接收时钟。 当累积的数据大小变得低于低阈值时，以较低的频率生成接收时钟。 基于从接收时钟发生电路8馈送的接收时钟，音频/视频解码器7解码来自接收缓冲器6的音频/视频数据。 本发明有利地适用于用于发送和接收TV广播信号的电视发射和接收系统。

公开(公告)号：US06992990B2

公开(公告)日：2006-01-31

申请号：US09904281

申请日：2001-07-12

申请人： Kenichi Sakusabe

发明人： Kenichi Sakusabe

IPC分类号： H04B3/36

CPC分类号： H03D3/007 ,  H03C3/40 ,  H04B1/0071 ,  H04B1/1027 ,  H04B7/12 ,  H04L1/0001

摘要： Radio communication apparatus includes a baseband processor for modulating data to be transmitted into an IF signal and for demodulating an IF signal derived from a received high frequency signal. A front end section receives the IF signal from the baseband processor and converts that IF signal into a high frequency signal for transmission. The front end section also is adapted to receive a high frequency signal from a remote location, and converts the received high frequency signal into an IF signal that is supplied to the baseband processor for demodulation and data recovery. The front end section is operable in a plurality of frequency bands and is tunable to a frequency within a selected one of the frequency bands for use as a radio frequency channel. Consequently, the number of simultaneously assigned channels in the same area can be markedly increased and the possibility of interrupting a communication link is significantly reduced.