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    Memory element with positive temperature coefficient layer
    1.
    发明授权
    Memory element with positive temperature coefficient layer 有权
    存储元件具有正温度系数层

    公开(公告)号：US07983068B2

    公开(公告)日：2011-07-19

    申请号：US12030059

    申请日：2008-02-12

    申请人： Klaus-Dieter Ufert

    发明人： Klaus-Dieter Ufert

    IPC分类号： G11C11/00

    CPC分类号： H01L45/08 ,  G11C7/04 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/56 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

    摘要： An integrated circuit including a memory element and method for manufacturing the integrated circuit are described. In some embodiments, the memory element includes a switching layer that selectively switches between a low resistance state and a high resistance state, and a positive temperature coefficient layer in thermal contact with the switching layer, the positive temperature coefficient layer having a resistance that increases in response to an increase in temperature.

    摘要翻译： 描述了包括存储元件的集成电路和用于制造集成电路的方法。 在一些实施例中，存储元件包括选择性地在低电阻状态和高电阻状态之间切换的开关层和与开关层热接触的正温度系数层，正温度系数层具有增加的电阻 响应温度升高。

    Memory Element with Positive Temperature Coefficient Layer
    2.
    发明申请
    Memory Element with Positive Temperature Coefficient Layer 有权
    具有正温度系数层的存储元件

    公开(公告)号：US20090201716A1

    公开(公告)日：2009-08-13

    申请号：US12030059

    申请日：2008-02-12

    申请人： Klaus-Dieter Ufert

    发明人： Klaus-Dieter Ufert

    IPC分类号： G11C11/00 ,  H01L29/02 ,  H01L21/00

    CPC分类号： H01L45/08 ,  G11C7/04 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/56 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

    摘要： An integrated circuit including a memory element and method for manufacturing the integrated circuit are described. In some embodiments, the memory element includes a switching layer that selectively switches between a low resistance state and a high resistance state, and a positive temperature coefficient layer in thermal contact with the switching layer, the positive temperature coefficient layer having a resistance that increases in response to an increase in temperature.

    摘要翻译： 描述了包括存储元件的集成电路和用于制造集成电路的方法。 在一些实施例中，存储元件包括选择性地在低电阻状态和高电阻状态之间切换的开关层和与开关层热接触的正温度系数层，正温度系数层具有增加的电阻 响应温度升高。

    Non-Volatile Memory Element with Improved Temperature Stability
    3.
    发明申请
    Non-Volatile Memory Element with Improved Temperature Stability 审中-公开
    具有改善温度稳定性的非易失性存储元件

    公开(公告)号：US20090200535A1

    公开(公告)日：2009-08-13

    申请号：US12030070

    申请日：2008-02-12

    申请人： Klaus-Dieter Ufert

    发明人： Klaus-Dieter Ufert

    IPC分类号： H01L45/00

    CPC分类号： G11C13/0011 ,  G11C7/04 ,  G11C2213/71 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/1625 ,  H01L45/1658 ,  H01L45/1675

    摘要： An integrated circuit including a memory element is described. The memory element includes a solid electrolyte layer that includes a matrix material having a metal dissolved therein, and a dopant distributed in the matrix material, the dopant competing with the metal to bind with elements of the matrix material at a crystallization temperature so that at least a portion of the metal in the matrix material remains unbound, to increase the temperature stability of the memory element.

    摘要翻译： 描述了包括存储元件的集成电路。 存储元件包括固体电解质层，其包括溶解有金属的基质材料和分布在基质材料中的掺杂剂，掺杂剂与金属竞争，在结晶温度下与基质材料的元素结合，使得至少 基体材料中的金属的一部分保持未结合，以增加存储元件的温度稳定性。

    Integrated circuit including resistivity changing memory cells
    5.
    发明授权
    Integrated circuit including resistivity changing memory cells 失效
    集成电路包括电阻率变化记忆单元

    公开(公告)号：US07538411B2

    公开(公告)日：2009-05-26

    申请号：US11411994

    申请日：2006-04-26

    申请人： Josef Willer ,  Klaus-Dieter Ufert

    发明人： Josef Willer ,  Klaus-Dieter Ufert

    IPC分类号： H01L29/00

    CPC分类号： H01L45/14 ,  B82Y10/00 ,  G11C13/00 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/32 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1675 ,  H01L45/1683

    摘要： Wordline stacks are arranged parallel at a distance from one another on a substrate surface. Bitlines are arranged transversely to the wordline stacks at a distance from one another. Source/drain regions are formed as doped regions in the vicinity of the wordline stacks. A resistive layer is disposed between a plurality of the source/drain regions and the bitlines and formed of a material having a resistance that is switched by an applied voltage. Source lines are arranged parallel to the wordline stacks so that they connect further pluralities of the source/drain regions.

    摘要翻译： 字线堆叠在衬底表面上彼此间隔一定距离平行排列。 位线横向于彼此间隔一定距离的字线堆栈布置。 源极/漏极区域形成为字线堆叠附近的掺杂区域。 电阻层设置在多个源极/漏极区域和位线之间，并且由具有通过施加电压切换的电阻的材料形成。 源极线平行于字线堆栈布置，使得它们连接更多个源极/漏极区域。

    Method for improving the thermal characteristics of semiconductor memory cells
    6.
    发明授权
    Method for improving the thermal characteristics of semiconductor memory cells 失效
    改善半导体存储单元的热特性的方法

    公开(公告)号：US07483293B2

    公开(公告)日：2009-01-27

    申请号：US11261212

    申请日：2005-10-28

    申请人： Cay-Uwe Pinnow ,  Klaus-Dieter Ufert

    发明人： Cay-Uwe Pinnow ,  Klaus-Dieter Ufert

    IPC分类号： G11C11/00

    CPC分类号： H01L45/1658 ,  G11C13/0011 ,  H01L45/085 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143

    摘要： A non-volatile, resistively switching memory cell includes a first electrode, a second electrode and a solid electrolyte, which is arranged such that it makes contact between the electrodes, and is composed of an amorphous or partially amorphous, non-oxidic matrix and a metal which is distributed in the amorphous or partially amorphous, non-oxidic matrix and whose cations migrate to the cathode in the amorphous or partially amorphous, non-oxidic matrix under the influence of an electrical voltage, wherein the solid electrolyte contains one or more further metallic materials for stabilization of the amorphous state of the matrix.

    摘要翻译： 非易失性电阻开关存储单元包括第一电极，第二电极和固体电解质，其被布置成使得其在电极之间接触，并且由无定形或部分无定形的非氧化基质和 分布在非晶或部分无定形非氧化基质中的金属，其阳离子在电压的影响下迁移至无定形或部分无定形非氧化基质中的阴极，其中固体电解质含有一种或多种 金属材料用于稳定基体的非晶状态。

    Resistively switching memory
    7.
    发明授权
    Resistively switching memory 失效
    电阻切换存储器

    公开(公告)号：US07442605B2

    公开(公告)日：2008-10-28

    申请号：US11113332

    申请日：2005-04-25

    申请人： Klaus Dieter Ufert ,  Cay-Uwe Pinnow

    发明人： Klaus Dieter Ufert ,  Cay-Uwe Pinnow

    IPC分类号： H01L21/82

    CPC分类号： G11C13/0011 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/1658 ,  H01L45/1675

    摘要： The present invention relates to a reproducible conditioning during the manufacturing of a resistively switching CBRAM memory cell comprising a first electrode and a second electrode with an active material positioned therebetween. The active material is adapted to be placed in a more or less electroconductive state by means of electrochemical switching processes. A CBRAM memory cell manufactured pursuant to the method according to the invention has, due to the improved conditioning, more reliable and more distinctly evaluable electrical switching properties. Moreover, no more forming step is necessary with the method according to the present invention.

    摘要翻译： 本发明涉及在制造电阻切换CBRAM存储单元期间的可再现调节，其包括第一电极和位于其间的活性材料的第二电极。 活性材料适于通过电化学切换工艺置于或多或少的导电状态。 根据本发明的方法制造的CBRAM存储单元由于改进的调理，具有更可靠和更明显的可评估电开关特性。 此外，根据本发明的方法不需要更多的成型步骤。